Commit Graph

482 Commits (b2d86bab470de365789ea35ff8d57de59266b391)

Author SHA1 Message Date
Laszlo Nagy bed5ce516c adcfifo/dacfifo: fix alignments 2019-01-23 14:45:45 +02:00
Laszlo Nagy a3766b464b adcfifo/dacfifo: Use proc to create infrastructure
Create the dacfifo/adcfifo infrastructure with procedures.
This will allow moving the parameters of the dac/adcfifo inside
the block design so it can be calculated based on other parameters.
2019-01-23 14:45:45 +02:00
Adrian Costina 70fe72da16 a10soc: Common, increase SPI frequency to 10MHz 2018-11-27 15:31:21 +02:00
Adrian Costina 52085c1739 a10soc: set "FORCE ALL USED TILES TO HIGH SPEED" 2018-11-27 15:31:21 +02:00
AndreiGrozav 9c6da0ff45 zed, zc702, zc706, ccfmc: Send video trough axis interface 2018-09-27 11:45:28 +03:00
Istvan Csomortani 985f35225c sys_gen: Remove deprecated script 2018-08-23 18:41:48 +03:00
AndreiGrozav 4f1c748d8a common/zc702: Replace VDMA with ADI DMAC 2018-08-20 14:28:01 +03:00
AndreiGrozav 6ef268bb31 common/zc706: Replace VDMA with ADI DMAC 2018-08-20 14:28:01 +03:00
AndreiGrozav a0e3997687 common/zed_system_bd.tcl: Replace VDMA
Replace Xilinx VDMA IP with ADI axi_dmac IP.
2018-08-20 14:28:01 +03:00
AndreiGrozav 1c75c7b9ca common/mitx045: Remove carrier support 2018-08-16 10:05:02 +03:00
AndreiGrozav ebae8bf8c1 Remove interrupts from system_top for all xilinx projects
- remove interrupts from system_top
- for all suported carriers:
	- remove all interrupt bd pins
	- connect to GND all initial unconnected interrupt pins
- update ad_cpu_interrupt procedure to disconnect a interrupt from GND
before connectiong it to another pin.
2018-08-10 10:10:58 +03:00
AndreiGrozav 74288cf9cb axi_hdmi_tx: Added INTERFACE parameter for selecting the interface type
Update all carriers/projects bd for configurable video interface:
- common zc702, zc706, zed
- adrv9361z7035/ccfmc_lvds
- imageon
2018-07-24 15:56:22 +03:00
Laszlo Nagy bcba21da71 zcu102: updated IOSTANDARD of Bank 44 IOs to match VCCO 3.3V 2018-06-05 08:52:50 +01:00
Lars-Peter Clausen 8a2a394790 Remove unused projects/common/Makefile
This file only references a subdirect that no longer exists, but nothing
else.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Rejeesh Kutty 8e042193be DE10: Initial commit
These modifications were taken from the old dev branch.
2018-04-11 15:09:54 +03:00
Rejeesh Kutty 72431ff952 a10soc: Connect AXI register reset 2018-04-11 15:09:54 +03:00
Laszlo Nagy fe2b43ddd9 base:constraint: Setting Configuration Bank Voltage Select
Set the properties to mirror the hardware configuration so
the Vivado tools can provide warnings if there are any conflicts
between configuration pin settings, such as an IOSTANDARD
on a multi-function configuration pin that conflicts with the
configuration voltage.
see:
https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf

The following base constraints were updated:
 - kcu105
 - kc705
 - vc707
 - ac701
2018-04-11 15:09:54 +03:00
Istvan Csomortani e3ea51ade3 avl_dacfifo: Refactor the fifo
+ Build both the read and write logic around an FSM
 + Consistent naming of registers and wires
 + Add support for burst lenghts higher than one, current burst lenght
is 64
 + Fix all the bugs, and make it work (first bring up with
adrv9371x/a10soc)
2017-10-31 14:30:06 +00:00
Adrian Costina d690a614c1 a10gx: Force all used tiles to high speed, in order to improve timing 2017-10-04 16:16:00 +01:00
STEVE KRAVATSKY ee01ea3736 daq2/a10gx: Add cfi_flash to qsys
+ Add cfi_flash to qsys
   + Set nios reset vector to cfi_flash
2017-10-04 11:30:29 +01:00
AndreiGrozav 256dd87dd2 common/microzed: Enable PS CLK1 = 200MHz 2017-09-25 15:16:58 +03:00
Istvan Csomortani 07f3295638 common/a10soc: Update configuration for emif plddr4 IP 2017-09-25 08:57:26 +01:00
AndreiGrozav 3a47567f9c common/a10gx: Chance SPI frequency from 128KHz to 10 MHz 2017-09-19 18:01:18 +03:00
AndreiGrozav b7ce81686a common/zcu102: Fix ps8 ref clock 0 frequency assignament 2017-08-22 15:37:59 +03:00
AndreiGrozav 41e247d426 common/zcu102: Add gpio_t connections 2017-08-22 15:37:59 +03:00
Istvan Csomortani c843a16797 microzed: Add a secondary 200 MHz clock for PS7 2017-08-18 10:14:21 +03:00
Rejeesh Kutty c632f4463f projects/zc702- free pmod gpio for customization 2017-08-09 14:06:26 -04:00
Lars-Peter Clausen 28801f2f37 common: a10soc: Use correct DDR memory reference clock type
The DDR memory reference clock on the A10SoC development board is
differential. Currently the EMIF core it is configured for single-ended
configuration, which causes it to generate incorrect IOSTANDARD
constraints. Those incorrect constraints get overwritten again in
system_assign.tcl, so things are working, but this generates a warning when
building the design

Configure the EMIF core correctly and remove the manual constraint overwrite since
they are no longer necessary.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-07 17:42:17 +02:00
Lars-Peter Clausen 7eba8326dd common: a10soc: Mark external reset as asynchronous
There is no guarantee that the external reset de-assertion is synchronous
to the sys_clk, yet the clock bridge marks the reset de-assertion as
synchronized to the clock. This can cause recovery or removal timing
violations for the registers affected by this reset signal and potentially
bring the system into an invalid state after the reset is de-asserted.

Mark the reset as not synchronized to the clock signal, this will make sure
that Qsys inserts the proper reset synchronizers where required.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-03 17:57:58 +02:00
Lars-Peter Clausen d7e87a60a9 Remove executable flag from non-executable files
All of these files are source code and are not executable standalone.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 17:56:07 +02:00
Lars-Peter Clausen 2c83cfff7e common: a10soc: Set IO standard for differential signal negative side
While things seem to work fine with only specifying the the IO standard for
the positive side of differential signals Quartus will issue a warning
about incomplete constraints if the IO standard is not specified for the
the neagtive side as well. To avoid these warnings add the missing
constraints.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 15:11:08 +02:00
Lars-Peter Clausen 5ffd1e1bac common: a10soc: Fix gpio_bd_i constraints
Fix a copy and paste error and specify the IO_STANDARD for all gpio_bd_i
rather than twice for half of them.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 15:11:08 +02:00
Adrian Costina 5a98e727f2 A10GX: Update DDR3 configuration 2017-07-27 12:38:14 +01:00
Nick Pillitteri 2d64d43475 ZCU102: SPI assign chip selects individually
Otherwise, Vivado 2016.4 sets all of the CSNs equal to CSN0. This fix is needed to get the FMCOMMS5 working properly on the ZCU102 (#36)
2017-07-21 09:22:10 +01:00
Lars-Peter Clausen 669a2da735 common: a10soc: Avoid unnecessary DMA clock domain crossing bridge insertion
Both the sys_hps.f2sdram_clock and the sys_dma_clk.clk signal are in the
same clock domain. They are both driven by the same clock. And even though
qsys is capable of detecting this it seems qsys interconnect is not able to
infer this and inserts a extra clock domain crossing bridge between the DMA
and the HPS AXI system memory interface.

To avoid this connect the sys_dma_clk.clk to the sys_hps.f2sdram_clock so
that all components are driven by the same qsys clock signal.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 19:45:27 +02:00
Istvan Csomortani b4a25223fa plddr3_dacfifo_bd: Increase the AXI burst length to max
Increase AXI burst length to maximum value, to support higher
data rates.
2017-07-06 10:15:06 +01:00
Adrian Costina d65a543854 kc705: Fix ethernet address span 2017-06-30 14:23:01 +03:00
AndreiGrozav a765a9c709 arradio: Add i2c interface 2017-06-29 17:26:58 +03:00
Rejeesh Kutty a23fb793a0 a5gt/a5soc - removed 2017-06-15 11:40:58 -04:00
Rejeesh Kutty ff646b0cfc common/a5soc- alt 16.1 updates 2017-06-13 09:54:01 -04:00
Rejeesh Kutty 2e17e67627 common/a5gt- altera 16.1 updates 2017-06-09 16:20:15 -04:00
Rejeesh Kutty ca536d50ac altera 16.1 c5soc updates 2017-06-08 15:03:03 -04:00
Rejeesh Kutty 5176e427a1 common/a10soc- add project create tcl procedure 2017-06-06 12:24:13 -04:00
Rejeesh Kutty 0bd22e78d9 altera- adi-project-create version 2017-06-05 15:24:35 -04:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Rejeesh Kutty 2d56141bbd altera- 2017-r1 16.1.2 2017-05-30 12:21:27 -04:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Rejeesh Kutty 0b3b1e6c76 kcu105- remove ethernet delay ctrl false path 2017-05-19 11:21:36 -04:00
Rejeesh Kutty f3959cb5b9 zcu102- 2016.4 updates 2017-05-18 14:17:20 -04:00
Rejeesh Kutty d507cd0c9a quartus optimization for frequency 2017-05-18 11:34:29 -04:00