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5931 Commits (b354d517f5881d4805312ef6f102093736ae3791)

Author SHA1 Message Date
Mihaita Nagy b354d517f5 daq2: Connected loose ad9144 dunf flag that fixes the critical warning 2021-08-20 10:38:52 +03:00
Adrian Costina 4cf53f373b Revert "adrv9009zu11eg: Integrate data_offload" 
This reverts commit 78999e154e.
The integration wasn't properly tested
 2021-08-19 21:43:09 +03:00
alin724 f8c82c611d axi_adrv9001: Add support for symbol operation mode on Xilinx devices 
Add CMOS support for the interface for the following symbol modes on Xilinx devices:

A              B  C       D                     E       F      G            H
CSSI__1-lane   1  16/8    80(SDR)/160(DDR)      80      -      SDR/DDR      SDR/DDR->4/2(C=16), 2/1(C=8)

Columns description:
A - SSI Modes
B - Data Lanes Per Channel
C - Serialization factor Per data lane
D - Max data lane rate(MHz)
E - Max Clock rate (MHz)
F - Max Sample Rate for I/Q (MHz)
G - Data Type
H - DDS Rate

CSSI - CMOS Source Synchronous Interface
 2021-08-17 15:33:06 +03:00
Laszlo Nagy 8afc03abab jesd204/ad_ip_jesd204_tpl_dac: Intel: Add support for AD916x preset files 2021-08-16 07:22:50 +03:00
stefan.raus 1f24344620 Update Quartus version to 20.4 
Update quartus compilation tools from 20.1 to 20.4.
Remove hardcoded version from axi_adrv9001 ip.
 2021-08-12 11:15:01 +03:00
AndreiGrozav b1d2a069e8 adi_make: Update bin build flow for 2020.1 tools 
The 2020.1 Xilinx tools have a different tcl procedures to build the boot.bin
file.
This commit updates the adi_make tcl flow for the new tools. The new
process is not backwards compatible with tools older than 2020 version.
 2021-08-10 17:44:30 +03:00
David Winter 235542cac9 data_offload: Fix support for > 4 GiB of storage 
This commit changes the transfer length register to work in increments of
64 bytes and without offset. The true transfer length can now be
determined by multiplying the value of the transfer_length register with
64.
A value of zero is interpreted as a request for all available storage.

Additionally, this commit fixes an off by one issue that was discovered
during testing of the RX path.

Signed-off-by: David Winter <david.winter@analog.com>
 2021-08-06 11:55:24 +03:00
David Winter 25038ccb4d data_offload: Fix MEM_SIZE parameter width 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-08-06 11:55:24 +03:00
David Winter 58953ff40d data_offload: Fix m_axis output stability issue 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-08-06 11:55:24 +03:00
David Winter 2b55c7453b data_offload: Fix duplicated output samples 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-08-06 11:55:24 +03:00
David Winter 04f2d19d4b data_offload: Fix data_offload getting stuck on oscillating m_saxis_ready 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-08-06 11:55:24 +03:00
David Winter 0af50d3f72 data_offload: Fix oneshot mode 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-08-06 11:55:24 +03:00
David Winter 66748510ea data_offload: write_fsm: Always transition out of idle on high init_req 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-08-06 11:55:24 +03:00
David Winter 9faef440b2 data_offload: Bump hdl version 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-08-06 11:55:24 +03:00
David Winter a89d0e6176 data_offload: Fix AXI register map 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-08-06 11:55:24 +03:00
David Winter e9e278c898 ad9081_fmca_ebz: Remove bypass gpio 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-08-06 11:55:24 +03:00
David Winter 537a284115 data_offload: Fix readme images 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-08-06 11:55:24 +03:00
David Winter 2178191610 ad9081_fmca_ebz: Switch util_dacfifo to data_offload engine 
Memory requirements are the same as with the dacfifo (1 MiB).

Signed-off-by: David Winter <david.winter@analog.com>
 2021-08-06 11:55:24 +03:00
Istvan Csomortani 6516b09a31 data_offload: Update README and generic block design 2021-08-06 11:55:24 +03:00
Istvan Csomortani 26518cdace data_offload: Add block diagrams 2021-08-06 11:55:24 +03:00
Istvan Csomortani 9b1108ea87 data_offload: Flush the DMA if the transaction size is bigger than the storage 2021-08-06 11:55:24 +03:00
Istvan Csomortani 564ef77588 data_offload: Calculate AXI_ADDRESS_LIMIT automatically 2021-08-06 11:55:24 +03:00
Istvan Csomortani c82b0fb420 data_offload: Delete fifo_dst_rlast 2021-08-06 11:55:24 +03:00
Istvan Csomortani 4026f2d414 daq2/zc706: PL DDR size is 1GByte 2021-08-06 11:55:24 +03:00
Istvan Csomortani 703cc8a17e data_offload_bd: Calculate the address limit from the address width 2021-08-06 11:55:24 +03:00
Istvan Csomortani 0436a82f4e data_offload: Fix alignment of write last beat and write full 2021-08-06 11:55:24 +03:00
Istvan Csomortani 378daf031c data_offload: Improve timing in regmap 2021-08-06 11:55:24 +03:00
Istvan Csomortani c27a0e4add data_offload: Fix fifo_dst_ready generation 2021-08-06 11:55:24 +03:00
Istvan Csomortani 78999e154e adrv9009zu11eg: Integrate data_offload 2021-08-06 11:55:24 +03:00
Istvan Csomortani dc910420bd daq2: Integrate data_offload 2021-08-06 11:55:24 +03:00
Istvan Csomortani 4c03580156 data_offload: Add integration process for Xilinx carriers 2021-08-06 11:55:24 +03:00
Istvan Csomortani 86b611c1f7 data_offload: Initial commit 2021-08-06 11:55:24 +03:00
Istvan Csomortani 6e97803437 ad_axis_inf_rx: Initialize output ports to avoid X propagation in simulation 2021-08-06 11:55:24 +03:00
Istvan Csomortani b9ac3a78a9 interfaces: Add XFER_REQ to fifo_rd_rtl.xml 2021-08-06 11:55:24 +03:00
Adrian Costina f2ca956d23 pluto: Fix dunf connection 2021-08-05 18:08:12 +03:00
Istvan Csomortani 157a8dee17 util_fifo2axi_bridge: Initial commit 2021-08-03 23:02:17 +03:00
Istvan Csomortani 0959c2bcad util_axis_fifo_asym: Initial commit 2021-08-03 23:02:17 +03:00
Nick Pillitteri 1543eb8881 axi_generic_adc: pass in number of channels instantiated to up_adc_common. Allows drivers/iio/adc/ad_adc.c driver to be used with this core. 
Signed-off-by: Nick Pillitteri <njpillitteri@gmail.com>
 2021-08-02 13:10:26 +03:00
stefan.raus bbb151f9f5 adi_project_xilinx.tcl: Set default value of ADI_USE_OOC_SYNTHESIS to 1 
In order to workaround optimization issues hit in Vivado 2020.2,
set ADI_USE_OOC_SYTHESIS variable by default to 1. This will build
projects in Out Of Context mode.
Projects can be build in Project Mode by exporting ADI_USE_OOC_SYTHESIS=n.
 2021-07-29 14:06:42 +03:00
stefan.raus 9d5de2fc21 Update Vivado version to 2020.2 
Update vivado version to 2020.2:
 - update default vivado version from 2020.1 to 2020.2
 - add conditions to apply specific contraints only in Out Of Context mode.
 - update DDR controler parameters for vcu118 and kcu105 dev boards
 2021-07-29 14:06:42 +03:00
Adrian Costina 907b750943 ad9083: Removed FIFO and increased DMAC transfer length 2021-07-28 12:45:20 +03:00
Isaac T 569257c4f3 Fix width of device_cfg_octets_per_multiframe 
The width of the parameter `device_cfg_octets_per_multiframe` doesn't match the width in the submodules and corresponding slave module jesd204_tx, resulting in a warning generated during validation in Vivado. This patch increases the width of this parameter in axi_jesd204_tx.
 2021-07-27 11:34:34 +03:00
Laszlo Nagy 20fc00a811 jesd204/ad_ip_jesd204_tpl_dac: Support for F=64 2021-07-27 11:31:19 +03:00
Laszlo Nagy c39b6b2ac8 jesd20r_rx/jesd204_tx: Support for F=64 2021-07-27 11:31:19 +03:00
Laszlo Nagy 4407d72d42 esd204/ad_ip_jesd204_tpl_adc: Support more datapath widths 2021-07-27 11:31:19 +03:00
Istvan Csomortani c808d8c3c7 ad_ip_jesd204_tpl_adc: Max number of lanes is 32 2021-07-27 10:28:48 +03:00
Istvan Csomortani f0027faf88 adi_jesd204: Add support of 16 lanes 2021-07-27 10:28:48 +03:00
Iacob_Liviu 8343c03f5c adrv9371x: remove IOB attribute from rx and rx_os 2021-07-26 12:42:21 +01:00
David Winter 1158538753 adi_board: Fix ad_connect command tracing 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-07-22 15:02:36 +03:00
David Winter 796af696da ad_fmclidar1_ebz: Remove invalid ad_connect invocations 
This commit removes two invalid ad_connect invocations, which weren't
caught in the original tests for commit cdda184007.

Signed-off-by: David Winter <david.winter@analog.com>
 2021-07-22 15:02:25 +03:00