Commit Graph

10 Commits (b354d517f5881d4805312ef6f102093736ae3791)

Author SHA1 Message Date
Laszlo Nagy 14307856ea xilinx:adxcvr: PRBS support
The new REG_PRBS_CNTRL and REG_PRBS_STATUS registers expose controls of internal
PRBS generators and checkers allowing the testing the multi-gigabit serial link
at the physical layer without the need of the link layer bringup.
2021-01-12 13:40:42 +02:00
Istvan Csomortani 363494ab9c library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 0d3e05b311 axi|util_adxcvr: Expose TX configurable driver ports
Expose the TX configurable driver ports, more specifically the
TX_DIFFCTRL, TX_POSTCURSORE and TX_PRECURSORE for software. This
provides a soft tunning capability of the transmit side of the
transceivers, in cases where the insertion loss of the channel is too
high or low, comparing to the default value supported by the default
configuration of the GTs.

You can find information about these configuration ports under the
section called 'TX Configurable Driver' in the GT transceivers user
guide. (UG476, UG576)
2018-10-04 14:37:02 +03:00
Istvan Csomortani 2602f239fa interfaces_ip.tcl: Delete trailing white spaces 2018-10-04 14:37:02 +03:00
Istvan Csomortani a386a42642 interface: Update the transceiver interfaces
On commit 6d4430 the signal called sel was removed from the transceiver
interfaces. Update the interface definition script.
2017-09-25 18:02:04 +01:00
Rejeesh Kutty 2ea997c3d5 interfaces- remove channel based pll reset 2016-11-22 11:34:29 -05:00
Rejeesh Kutty def47dd536 interfaces: added xcvr interfaces 2016-06-17 12:00:15 -04:00
Rejeesh Kutty 2b894bc13e up_gt: separate pll resets to tx/rx 2015-10-02 13:58:30 -04:00
Rejeesh Kutty 2345be2237 interfaces-- transceiver cores 2015-08-14 15:33:36 -04:00
Rejeesh Kutty af87b65788 interfaces_ip: added 2015-08-14 11:24:27 -04:00