Commit Graph

37 Commits (b38747cefc08fc792c14c6fb0df8db3c4c2ad5d4)

Author SHA1 Message Date
stefan.raus 4a772265a9 Update Quartus Prime version from 19.3.0 to 20.1.0
adi_project_intel.tcl: Change quartus version to 20.1.0.
library: Set qsys version so that IP instances won't require a specific version.
2021-03-08 11:29:33 +02:00
Istvan Csomortani 53e07c5d29 quartus_pro: Parameter property TYPE is not supported 2020-08-11 10:14:18 +03:00
Laszlo Nagy 70d139af7f jesd204/ad_ip_jesd204_tpl_dac: Fix Intel dependencies
Even if the IQ rotation is disabled in the projects all modules has to be
added to the list of dependencies to avoid compilation errors.
2020-04-08 10:50:28 +03:00
Istvan Csomortani 0f7a3b953a scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface 2019-06-29 06:53:51 +03:00
Istvan Csomortani 5329458a62 library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 79b6ba29ce all: Rename altera to intel 2019-06-29 06:53:51 +03:00
AndreiGrozav 66823682b6 Add FPGA info parameters flow
Common basic steps:
- Include/create infrastructure:

   * Intel:
       - require quartus::device package
       - set_module_property VALIDATION_CALLBACK info_param_validate

   * Xilinx
       - add bd.tcl, containing init{} procedure. The init procedure will be
         called when the IP will be instantiated into the block design.
       - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl
       - create GUI files

- add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params)
- add/propagate the info parameters through the IP verilog files

axi_clkgen
util_adxcvr
ad_ip_jesd204_tpl_adc
ad_ip_jesd204_tpl_dac
axi_ad5766
axi_ad6676
axi_ad9122
axi_ad9144
axi_ad9152
axi_ad9162
axi_ad9250
axi_ad9265
axi_ad9680
axi_ad9361
axi_ad9371
axi_adrv9009
axi_ad9739a
axi_ad9434
axi_ad9467
axi_ad9684
axi_ad9963
axi_ad9625
axi_ad9671
axi_hdmi_tx
axi_fmcadc5_sync
2019-03-30 11:26:11 +02:00
Laszlo Nagy ca1ba6a6fe axi_ad9144/axi_ad9152: patch up_tpl_common dependency 2019-02-01 08:28:28 +00:00
Laszlo Nagy 8bce4c5b0a jesd204_tpl: update address widths of TPL instances 2018-12-04 14:02:22 +02:00
Lars-Peter Clausen b7ea846c40 ad_ip_jesd204_tpl_dac: Use perfect shuffle helper module
Replace the open-coded instances of a perfect shuffle in the DAC framer with
the new helper module.

Using the helper module gives well defined semantics and hopefully makes
the code easier to understand.

There are no changes in behavior.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-10-15 15:34:31 +03:00
Lars-Peter Clausen 870d09d44d axi_ad91{44,52}: hw.tcl: Add missing file
Commit 5d044b9fd3 ("ad_ip_jesd204_tpl_dac: Share PN sequence generator
between all channels") add a new file to the ad_ip_jesd204_tpl_dac, but
neglected to update the hw.tcl for the axi_ad9144 and axi_ad9152 which use
this file.

The result is that Intel project using these cores currently do not build.

Fix it by adding the missing file to the file list.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-08-23 18:35:30 +03:00
AndreiGrozav d27ed93594 axi_ad9144: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00
Lars-Peter Clausen 0072476ad1 axi_ad9144: Use the generic JESD204 DAC transmitter core
Replace the axi_ad9144 implementation with the new generic JESD204
interface DAC core. The replacement is functionally equivalent.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-02 17:21:20 +02:00
Lars-Peter Clausen bd251a5fd5 Remove unused DMA overflow signal from DAC DMA interfaces
The DAC DMA will never overflow and unsurprisingly the dac_dovf signal is
never used anywhere. It is very unlikely it will ever be used, so remove
it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-02 17:21:20 +02:00
Lars-Peter Clausen fa9d94bfe8 avl_adxcvr: Perform octet order swap
The ADI transport layer peripherals expect the first octet to be in the
LSBs and the last octet to be in the MSBs. The Altera JESD204 core orders
the octets the other way around though, first octet in the MSBs and last
octet in the LSBS.

Currently this is handled by having each transport layer peripheral swap
the octets around when it is connected to the Altera JESD204 core.

Change this so that rather than having to do the data swizzling in every in
every transport layer peripheral perform it at the input/output of the link
layer peripheral inside the generated block.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-03 17:57:58 +02:00
Lars-Peter Clausen 154e40eaaa axi_ad9144: axi_ad9144_hw.tcl: Disable unused interfaces instead of not creating them
Currently the axi_ad9144_hw.tcl script does not create interfaces if they
are not used in the current configuration. This has the disadvantage that
the ports belonging to these interfaces are not included in the generated
HDL wrapper. Which will generate a fair bunch of warnings when synthesizing
the HDL.

Instead always generate all interfaces, but disable those that are not used
in the current configuration. This will make sure that the ports belonging
to these interfaces are properly tied-off in the generate wrapper HDL.

This reduces the amount of false positive warnings generated and makes it
easier to spot actual issues.

While we are at it also use a loop to create the interfaces since they all
follow the same pattern.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 15:21:02 +02:00
Lars-Peter Clausen d7e87a60a9 Remove executable flag from non-executable files
All of these files are source code and are not executable standalone.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 17:56:07 +02:00
Lars-Peter Clausen bd8d676346 library: Use ad_ip_intf_s_axi were applicable
Use the ad_ip_intf_s_axi helper function to create the axi4lite slave
interface for memory mapped peripherals. This slightly reduces the amount
of boilerplate code in the peripheral's *hw.tcl

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-24 15:52:37 +02:00
Istvan Csomortani 10898d6618 constraints: Split the regmap CDC constraint into separate file 2017-05-25 15:12:16 +03:00
Rejeesh Kutty c728299e71 altera- default to latest version 2017-05-12 13:25:17 -04:00
Rejeesh Kutty bced17a16f axi_ad9144- qsys updates 2016-09-12 14:57:50 -04:00
Istvan Csomortani df36902713 lib_refactoring: Fix path of the IO macros 2016-08-08 15:07:19 +03:00
Rejeesh Kutty d254fa841b library- altera updates 2016-05-23 10:55:07 -04:00
Rejeesh Kutty ff1d98a0c7 ad9144: duplicate include 2015-12-10 16:02:35 -05:00
Adrian Costina f51871c1e4 axi_ad9144: Updated altera interfaces, added FIFO conduits per channel 2015-11-24 11:44:07 +02:00
Istvan Csomortani 57cfb7cfb1 hdl/library: Update the IP parameters
The following IP parameters were renamed:

PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
Rejeesh Kutty 3101045109 qsys- library group 2015-07-17 10:07:15 -04:00
Rejeesh Kutty 60c344cea6 ad9144- qsys needs interface signal name matching 2015-07-15 15:59:51 -04:00
Rejeesh Kutty c69e36314c ad9144- remove avalon streaming 2015-07-13 10:03:16 -04:00
Rejeesh Kutty e02273781f ad_rst- non lpm version 2015-06-04 10:53:12 -04:00
Rejeesh Kutty 91b0f70972 library: remove drp cntrl 2015-06-02 09:58:57 -04:00
Rejeesh Kutty d7b68c39ef altera- sdc 2015-06-01 10:59:59 -04:00
Rejeesh Kutty e05ff26406 ad9144: ddata-typo 2015-05-21 14:06:09 -04:00
Rejeesh Kutty 465f7dff88 library/util_jesd_align -added 2015-05-20 15:38:43 -04:00
Rejeesh Kutty da0409b5a6 library- qsys components 2015-05-20 11:51:50 -04:00
Rejeesh Kutty 9b425736ac library: altera ip modifications 2015-05-20 10:41:21 -04:00
Rejeesh Kutty 553f89f59d ad9144- add hw tcl 2015-05-12 14:39:57 -04:00