b3ce821311
change pl ddr clock to 1G
2017-05-01 09:35:10 -04:00
fa794520fd
kc705_common/adv7511: Update IP instantiations
2017-04-21 15:03:31 +03:00
6ed721ee66
adrv9371/a10soc: Integrate the avl_dacfifo into project
2017-04-21 13:27:35 +03:00
2379514ae6
ac701_common/adv7511: Update IP instantiations
...
IPs are instantiated using the ad_ip_instance process, and configured
with the ad_ip_paramter process, to facilitate the tool upgrade.
2017-04-21 13:16:25 +03:00
bb0021a926
common: zed/zc702/zc706/mitx045: audio_clkgen: Disable phase alignment
...
There is no need for the audio clock to be phase aligned to its source
clock. When phase alignment is disabled the MMCM uses an internal feedback
path without requiring external resources, so disable it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 18:12:24 +02:00
bfcc3696e4
common: zed/zc702/zc706/mitx045: Set audio clkgen clock source type
...
Depending on the configuration of the clock source type of the input clock
the clocking wizard will instantiate all kinds of buffers on the input
clock signal.
For these particular projects there is no need to add any kind of buffer
since the source is already coming from a global clock buffer. So set the
configuration accordingly.
Avoids the following warning:
[Opt 31-32] Removing redundant IBUF since it is not being driven by a
top-level port. i_system_wrapper/system_i/sys_audio_clkgen/inst/clkin1_ibufg
Resolution: The tool has removed redundant IBUF. To resolve this
warning, check for redundant IBUF in the input design.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 18:12:24 +02:00
23ccc66f22
common: zc702/zc706/mitx045: audio_clkgen: Infer input clock frequency
...
Instead of manually specifying the input clock frequency let the core infer
it automatically. This makes it more straight forward to change the clock
frequency.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 18:12:24 +02:00
b213567305
common: zed: audio_clkgen: Infer input clock frequency
...
Instead of manually specifying the input clock frequency let the core infer
it automatically. This makes it more straight forward to change the clock
frequency.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-19 16:29:09 +02:00
71394ee465
kcu105: ip automatic version update
2017-04-18 11:59:54 +03:00
942d69a30c
Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU
2017-04-18 10:57:16 +03:00
20672a3a8b
mitx045: ip automatic version update
2017-04-14 17:46:25 +03:00
954037a716
microzed: ip automatic version update
2017-04-14 17:24:24 +03:00
1c23cf4621
all: Update verilog files to verilog-2001
2017-04-13 11:59:55 +03:00
627f78ec19
Ip automatic version update: common/board
...
- vc707
- zc702
- zed
2017-04-12 19:03:16 +03:00
2535165461
xilinx- ad-ip-instance & ad-ip-parameter
2017-04-06 13:04:19 -04:00
80f93e6a31
zc706- ad-ip-instance & ad-ip-parameter
2017-04-06 13:03:22 -04:00
deb8635854
adrv9371x/altera- gpio equivalency fix
2017-03-27 16:37:55 -04:00
4a275302a0
a5soc- add ddr3 location assignments
2017-03-22 10:12:34 -04:00
b3f06af77a
altera srf files do not work
2017-03-22 09:25:50 -04:00
66a5d44a18
a5gte- add constraints for tq
2017-03-21 10:53:31 -04:00
2e22ce3b62
a10gx- ignore preliminary timing model warnings
2017-03-21 10:52:28 -04:00
c7351f3ce3
arradio/c5soc- remove qsys files
2017-03-20 15:56:07 -04:00
589e6b53d8
arradio/c5soc- qsys-script flow
2017-03-20 15:42:33 -04:00
b39fecadd9
altera- ignore preliminary timing messages
2017-03-20 12:48:53 -04:00
7dfa8c599f
arradio/c5soc- updated to new framework/16.0
2017-03-20 12:15:18 -04:00
12f44ccbcc
arradio/c5soc- critical warnings fix
2017-03-20 12:14:21 -04:00
3fa9a30f0e
a10soc/plddr4- lower mem clk to meet timing
2017-03-06 14:12:25 -05:00
38a27d02f6
a10soc/plddr4- differential refclk
2017-03-06 14:11:36 -05:00
ec89b1a45f
altera/adrv9371x- add dacfifo
2017-03-01 15:52:07 -05:00
c1be17a3af
Altera a10 devices: disable warnings regarding unused channels
2017-03-01 11:32:17 +02:00
aad41039bd
a10soc- plddr4 settings
2017-02-28 13:36:28 -05:00
c1aac4a9fb
common: adc/dac fifo board designs
2017-02-27 16:06:39 -05:00
1fce57f6c3
axi_dacfifo: Redesign the bypass functionality
2017-02-23 17:32:31 +02:00
edd5e9570f
file renamed; sed output; fingers crossed
2017-02-22 15:56:37 -05:00
b00dc4b195
plddr3- change to board files
2017-02-22 15:22:50 -05:00
89b49d2f67
fifo- as board files
2017-02-22 15:18:50 -05:00
879ed64bb6
compression flag changes
2017-02-22 15:15:53 -05:00
754ac6a403
w/r-fifo- removed
2017-02-22 15:10:06 -05:00
a15e05c497
adcfifo- remove axi-byte-width parameter
2017-02-17 15:29:10 -05:00
cb3d1883bc
fmcjesdadc1/a5gt- hard placement of ddr hr/qr registers
2017-02-17 15:21:33 -05:00
95a4ea20c8
axi_dacfifo: Delete redundant parameter BYPASS_EN
2017-02-16 19:53:44 +02:00
c39ed08edd
zcu102/*- actual clock == desired clock
2017-02-06 12:53:47 -05:00
be1328c55b
kcu105- added missing ethernet configurations
2017-01-23 10:14:09 -05:00
18660c7ab4
fmcjesdadc1/a5gt: ddr3 use ip constraints
2016-12-22 14:14:21 -05:00
1ceec2e2a9
projects/a5gt- use 50m afi clock for cpu- xcvr reconfig timing
2016-12-22 14:14:21 -05:00
eba30b0cde
projects/altera- qii_auto_pack option
2016-12-22 14:14:21 -05:00
4a783d523d
projects/altera* - default & common qsys commands
2016-12-20 16:27:44 -05:00
9fb7db97da
a5gte: Fixed timing violations
2016-12-13 10:30:24 +02:00
8ebc8fe4e2
updated makefiles
2016-12-09 23:06:41 +02:00
8e69c838e1
common/ac701: Connect axi_ddr_cntrl/device_temp_i to GND
2016-12-09 13:54:39 +02:00
Rejeesh Kutty
Istvan Csomortani
Lars-Peter Clausen
Adrian Costina
AndreiGrozav