21 Commits (b3ce821311a7fb8f0e55062d278a40f815f6edfa)

Author	SHA1	Message	Date
Rejeesh Kutty	b3ce821311	change pl ddr clock to 1G	2017-05-01 09:35:10 -04:00
Istvan Csomortani	6ed721ee66	adrv9371/a10soc: Integrate the avl_dacfifo into project	2017-04-21 13:27:35 +03:00
Rejeesh Kutty	deb8635854	adrv9371x/altera- gpio equivalency fix	2017-03-27 16:37:55 -04:00
Rejeesh Kutty	b3f06af77a	altera srf files do not work	2017-03-22 09:25:50 -04:00
Rejeesh Kutty	b39fecadd9	altera- ignore preliminary timing messages	2017-03-20 12:48:53 -04:00
Rejeesh Kutty	3fa9a30f0e	a10soc/plddr4- lower mem clk to meet timing	2017-03-06 14:12:25 -05:00
Rejeesh Kutty	38a27d02f6	a10soc/plddr4- differential refclk	2017-03-06 14:11:36 -05:00
AndreiGrozav	c1be17a3af	Altera a10 devices: disable warnings regarding unused channels	2017-03-01 11:32:17 +02:00
Rejeesh Kutty	aad41039bd	a10soc- plddr4 settings	2017-02-28 13:36:28 -05:00
Rejeesh Kutty	6b492b79db	a10soc - remove default assignments	2016-11-04 15:01:19 -04:00
Rejeesh Kutty	50552ce7d6	adrv9371x- altera updates	2016-10-27 09:25:00 -04:00
Rejeesh Kutty	f752f0c9d7	a10soc- xcvr updates	2016-10-27 09:25:00 -04:00
Adrian Costina	e40311eee9	adrv9371x: A10soc, connected DMAs through 128 bit SDRAM0 port at 175MHz	2016-09-29 09:14:37 +01:00
Adrian Costina	2d307d5f58	a10soc: Added system reset bridge. Using F2SDRAM port used in the previous Qsys design	2016-09-24 10:06:35 +03:00
Adrian Costina	143423e3b9	adrv9371x: A10SOC, fix Makefile and system scripts to be compatible with altera	2016-09-21 18:13:02 +03:00
Adrian Costina	40c9fc92c1	a10soc: Switched to tcl flow	2016-09-08 11:31:06 +03:00
dbogdan	4658686ae1	adrv9371x/a10soc: Misc changes for being able to run Linux	2016-08-16 11:56:25 +03:00
Rejeesh Kutty	92dcce1674	a10soc: default ports	2016-05-04 13:42:12 -04:00
Rejeesh Kutty	e790e4c3ae	a10soc- complete qsys	2016-04-25 12:56:19 -04:00
Rejeesh Kutty	d36d1263c5	a10soc- updates	2016-04-25 10:50:09 -04:00
Rejeesh Kutty	82c4f75f13	a10soc- a10gx copy	2016-04-22 10:39:21 -04:00