Commit Graph

5199 Commits (b5dfdcfb8447fbae72aefe04d389fef38d941847)

Author SHA1 Message Date
AndreiGrozav b5dfdcfb84 axi_adc_trigger: Add cascade support.
- Add embedded trigger as an option. The use of the embedded trigger as an
option in the data stream is done for further processing, keeping the data
synchronized with the trigger.
When instrument (module) trigger is desired (logic_analyzer - adc_trigger),
a small propagation time is required, hence the need to remove the
util_extract(trigger extract) module from the data path.

- Add more options for the IO triggering. This will open the door for multiple
M2k synchronization(triggering).
trigger_o mux:
1 - trigger flag (from regmap)
2 - external pin trigger (Ti)
3 - external pin trigger (To)
4 - internal adc trigger
5 - logic analyzer trigger

The signal passed to trigger_o must not be delayed, but the new value has to be
kept for a short period, 1ms (100000 clock cycles), to reduce switch noises in
the system.

The axi_adc_trigger handles 3 output triggers:
- trigger_o - external trigger (1 clock cycle delay)
- trigger_out - signals on dmac/fifo_wr_sync the start of a new transfer.
A variable fifo depth is present in the data path, which delays the data
arriving at the DMA with 3 clock cycles. By coincidence, the external trigger
is synchronized and detected on 3 clock cycles. To get a maximum optimization
the trigger_out will be delayed with 3 clock cycles for internal triggers and
directly forwarded in the case of an external trigger.
- trigger_out_la (cascade trigger for logic_analyzer - m2k example)

Because the trigger_out_la must have a small delay, to get a realible
instrument triggering mechanism, a 1 delay clock cycle must be added on the
trigger paths, to avoid creating a closed combinatorial loop.

Increase pcore version. The major version 3 is used to describe the instrument
trigger updates.
2019-08-22 18:06:10 +03:00
Arpadi baacc906a6 ad7616_bugfix: read data multiplexation 2019-08-22 17:59:00 +03:00
Nick Pillitteri b77f922de0 axi_generic_adc: infer clock for input adc_clk 2019-08-22 10:39:59 +03:00
AndreiGrozav 78afe38a3f adrv9009: Add decimation and interpolation filters 2019-08-20 16:24:47 +03:00
AndreiGrozav 44deaadb4a adrv9371: Add decimation and interpolation filters 2019-08-20 16:24:47 +03:00
AndreiGrozav 36a1767329 Add generic fir filters processes for RF projects 2019-08-20 16:24:47 +03:00
Laszlo Nagy 0261eade0c zynq:all: fix SPI clock constraint
According to data sheets the EMIO SPI controller maximum frequency is
just 25MHz. Constrain the SPI clock accordingly.
2019-08-09 16:39:56 +03:00
Laszlo Nagy 7f72340be8 axi_dmac: fix timing constraints
When source clock is asynchronous to request clock the rewind request
handshake block must be constrained based on request clock domain.
2019-08-08 14:26:07 +03:00
Istvan Csomortani 6fad82c329 ad_fmclidar1_ebz/zc706: Define device clock and SYSREF timing relation 2019-08-08 14:26:07 +03:00
Istvan Csomortani 056c43dc98 axi_laser_driver: Set default value for sequencer offset 2019-08-08 14:26:07 +03:00
Istvan Csomortani d43e6ee239 axi_laser_driver: TIA's are controlled individually in manual mode
Update the sequencer, so the TIA channel selection can be controlled separately
for each TIA, when the sequencer runs in manual mode.
2019-08-08 14:26:07 +03:00
Istvan Csomortani ea158ee42b ad_fmclidar_ebz: Fix AFE's SPI interface connection 2019-08-08 14:26:07 +03:00
Istvan Csomortani 3290838743 ad_fmclidar1_ebz: Add a dummy ADC channel with TIA channel info
Software has to know which TIA channel was used for a particular capture.
Define an additional dummy ADC channel which will provide this
information. Currently this channel is always enabled.
2019-08-08 14:26:07 +03:00
Istvan Csomortani d096b8f6f4 ad_fmclidar1_ebz: Move the util_axis_syncgen into common direcotry 2019-08-08 14:26:07 +03:00
Istvan Csomortani ea18636586 ad_fmclidar1_ebz: Connect the TIA sequencer to the GPIOs 2019-08-08 14:26:07 +03:00
Istvan Csomortani 21bbc900c8 ad_fmclidar1_ebz: Initial commit
This commit was created by squashing the following commits, these
messages were kept just for sake of history:

  ad9694_500ebz: Mirror the SPI interface to FMCB
  ad9694_500ebz: Set transceiver reference clock to 250
  ad9694_500ebz: Allow to configure number of lanes, number of converters
                 and sample rate
  axi_ad9694: Fix number of lanes, it must be 2
  ad9694_500ebz: Update the mirrored spi pin assignments
  ad9694_500ebz: Gate SPI MISO signals based on chip-select
  ad9694_500ebz: Set channel pack sample width
  ad9694_500ebz: Change reference clock location
  ad9694_500ebz: Remove transceiver memory map arbitration
  ad9694_500ebz: Ensure ADC FIFO DMA_DATA_WIDTH is not larger ADC_DATA_WIDTH
  ad9694_500ebz: Adjust breakout board pin locations
  ad_fmclidar1_ebz: Rename the ad9694_500ebz project
  ad_fmclidar1_ebz: Fix lane mapping
  ad_fmclidar1_ebz: Delete deprecated files
  ad_fmclidar1_ebz: Integrate the axi_laser_driver into the design
  ad_fmclidar1_ebz: OTW is an active low signal
  ad_fmclidar1_ebz: zc706: Fix iic_dac signals assignment
  ad_fmclidar1_ebz: Switch to util_adcfifo
  ad_fmclidar1_ebz: Enable synced capture for the fifo
  ad_fmclidar1_ebz/zc706: Enable CAPTURE_TILL_FULL
  ad_fmclidar1_ebz/zc706: Reduce FIFO size to 2kB
  ad_fmclidar1_ebz: Laser driver runs on ADC's core clock
  ad_fmclidar1_ebz_bd: Delete the FIFO instance

     Because the DMA transfers are going to be relatively small (< 2kbyte),
     the DMA can handle the data rate, even when the frequency of the laser
     driver pulse is set to its maximum value. (200 kHz)

     The synchronization will be done by connecting the generated pulse to
     the DMA's SYNC input. Although, to support 2 or 1 channel scenarios, we
     need to use the util_axis_syncgen module to make sure that the DMA
     catches the pulse, in cases when the pulse width is too narrow. (SYNC is
     captures when valid and ready is asserted)

     Also we have to reset the cpack IP before each pulse, to keep the DMA buffer's
     relative starting point in time fixed, when only 2 or 1 channel is
     active.
2019-08-08 14:26:07 +03:00
Istvan Csomortani 9422da7908 util_axis_syncgen: Initial commit
The module can receive a synchronous or asynchronous pulse with an arbitrary
width and generate a SYNC signal for the DMA Source AXI Streaming interface.

This way we can synchronize the DMA transfers to an external
pulse/signal.
2019-08-08 14:26:07 +03:00
Istvan Csomortani 75d1379618 axi_laser_driver: Initial commit
The laser driver contains the axi_pulse_gen's IP and an additional
register map which controls/monitor the laser driver enable control line
and the over temperature warning line (OTW).

It also contains an interrupt logic, which allows to generate an
interrupt in function of the generated pulse or incoming OTW signal.

The IPs register maps looks as follow:

0x00 - axi_pulse_gen register map
0x80 - axi_laser_driver register map
  0x80 - DRIVER_ENABLE
  0x84 - DRIVER_OTW
  0x88 - EXT_CLK_COUNTER
  0xA0 - IRQ_MASK
  0xA4 - IRQ_SOURCE
  0xA8 - IRQ_PENDING
  0xAC - SEQUENCER_CONTROL
         0 - SEQUENCER_ENABLE
         1 - AUTO_SEQUENCER_ENABLED
  0xB0 - SEQUENCER_SYNC_OFFSET
  0xB4 - AUTO_SEQUENCE
         [ 1: 0] - CHANNEL_SEL_0
         [ 5: 4] - CHANNEL_SEL_1
         [ 9: 8] - CHANNEL_SEL_2
         [13:12] - CHANNEL_SEL_3
  0xB8 - MANUAL_SEQUENCE
         [ 1: 0] - MANUAL_CHANNEL_SEL

Current interrupt sources scheme is:
    - bit 0 : pulse (triggered by the level of the pulse)
    - bit 1 : OTW_N enter (triggered by positive edge of the OTW_N)
    - bit 2 : OTW_N exit (triggered by the level of the pulse)

Generate a reset signal before the pulse which can be used to reset
various IP's of the data path (eg. pack/cpack). This can help to clear out the
internal buffers and registers of these IP, starting clean at the moment when
the actual pulse arrives.

The sequencer has an auto and a manual mode, and can be set to custom
sequences of the TIA channel selection lines sate.

The sequencer in auto mode is synchronized to the pulse, it will change
its state before a generated pulse which will drive the lasers. The
offset between the sequencer beat and the laser driver pulse can be
modified through an AXI register.
2019-08-08 14:26:07 +03:00
Istvan Csomortani d4200aee9a axi_pulse_gen_regmap: Rename the clk output to clk_out 2019-08-08 14:26:07 +03:00
Istvan Csomortani f1403aa593 axi_pulse_gen: Update constraint file
- add missing false paths
 - change the bus skew constraint to a false path, for some reason the
   tool does not change the path's requirement after a set_bus_skew
   constraint
2019-08-08 14:26:07 +03:00
Istvan Csomortani 3a7d0698a8 axi_pulse_gen: Registers should be placed at front of the register space
Because this register map will be integrated into other IPs too, make
sure that the registers are places in the absolute front of the register
space.
2019-08-08 14:26:07 +03:00
Istvan Csomortani 723f5cddfc util_pulse_gen: Expose the internal counter
Expose the internal counter so we can synchronize external signals to,
or relative to, the generated pulse.
2019-08-08 14:26:07 +03:00
Istvan Csomortani 544e2b8ad0 util_pulse_gen: Pulse should not be generated if module is in reset 2019-08-08 14:26:07 +03:00
Istvan Csomortani 75e4c844ba util_pulse_gen: Optimise design in order to improve timing 2019-08-08 14:26:07 +03:00
Arpadi 0680e44330 system_id: deployed ip 2019-08-06 16:53:11 +03:00
Sergiu Arpadi 4fe5f007cb system_id: added axi_sysid ip core and tcl 2019-08-06 16:53:11 +03:00
Arpadi ab3d43be71 up_axi.v: fixed bus width definition
fixed axi_dma_regmap.v bus width missmatch
2019-08-06 13:45:54 +03:00
Adrian Costina a78c95d8fb adrv9009_zu11eg_som: Add SPI clock constraint 2019-08-01 18:15:45 +03:00
Adrian Costina f2d2092297 axi_dacfifo: Add don't touch for the constraints to apply 2019-08-01 18:15:45 +03:00
AndreiGrozav c3739b1f30 Fix copy-paste typo in *_ip.tcl
- axi_ad9162
- axi_ad9434
- axi_ad9625
- axi_hdmi_tx
2019-07-29 15:37:30 +03:00
Arpadi fe09acaa2f up_axi_update: ADDRESS_WIDTH parameter is now a localparam
ADDRESS_WIDTH is now AXI_ADDRESS_WIDTH - 2;
up_axi instantiations will set AXI_ADDRESS_WIDTH instead of ADDRESS_WIDTH;
2019-07-26 11:58:58 +03:00
István Csomortáni 14a4acfd0e
projects/scripts: Fix a typo in adi_env.tcl 2019-07-25 17:58:36 +03:00
Istvan Csomortani fa610d36c6 ad_ghdl_dir: Fix global variable name
In #PR318 the global variable $ad_phdl_dir name were changed to
$ad_ghdl_dir.
2019-07-23 10:29:37 +01:00
Adrian Costina 6655829bc7 daq2: VC707: Remove project 2019-07-22 13:25:46 +01:00
Adrian Costina a6cff0f804 motcon2_fmc: Remove project 2019-07-22 13:23:43 +01:00
Istvan Csomortani 6a721c0bf0 adi_env: Update system level environment variable definition
Our internal repository was changed from phdl to ghdl. Update the
adi_env.tcl scripts and other scripts, which depends on the $ad_ghdl_dir
variable. This way the tools will see all the internal IPs too.
2019-07-22 11:00:45 +03:00
AndreiGrozav ce5aadb3e4 adrv9361z7035/common/ccbox_constr.xdc: Cosmetics only 2019-07-17 10:37:30 +03:00
AndreiGrozav 6f627c2105 adrv9361z7035/ccbox: Keep by default in powerdown the 12V PS
Because of build hazards, the power supply can be randomly powered on,
when the pin is left in high impedance.
2019-07-17 10:37:30 +03:00
Istvan Csomortani 3031ec3bdd adi_jesd204: Move some leftover files to intel directory
These file were left in the old library directory, move them to the new
library/intel directory.
2019-07-10 10:57:12 +01:00
AndreiGrozav 5f1cb18c9b ad7616_sdz/zc706: Fix Build
- Fix typo
- Remove the unused(old flow) ps interupts
2019-07-10 12:51:42 +03:00
Laszlo Nagy 1f1b2b4fa3 axi_dmac:axi_dmac_ip: Fix AXI Stream signals bundle
The unused AXI stream signals have to be added to the AXIS interface so
they don't hang loose on the IP in the block design.
2019-07-08 16:08:06 +03:00
Istvan Csomortani bb8912b766 axi_hdmi_tx: Update parameter name 2019-06-29 06:53:51 +03:00
Istvan Csomortani 165c8a943b gitignore: Update to the new naming convention 2019-06-29 06:53:51 +03:00
Istvan Csomortani e1d9a36ae0 scripts/adi_project_intel: Rename ALT_NIOS_MMU_ENABLED to NIOS_MMU_ENABLED 2019-06-29 06:53:51 +03:00
Istvan Csomortani 76620bc890 avl_adxcvr: Rename variables with alt_* pre-fix
- alt_sys_clk -> sys_clk
  - alt_xcvr_rst -> xcvr_rst
  - alt_ref_clk -> ref_clk
  - alt_fpll_rst_cntrol -> fpll_rst_control
  - alt_core_pll -> core_pll
  - alt_core_clk -> core_clk
  - alt_rst_cntrol -> rst_control
  - alt_lane_pll -> lane_pll
  - alt_ip -> jesd204_ip
  - alt_xphy -> avl_xphy
  - alt_phy_* -> phy_*
2019-06-29 06:53:51 +03:00
Istvan Csomortani 6a42f54b1e axi_ad9361/intel: Rename varibles with alt_* pre-fix 2019-06-29 06:53:51 +03:00
Istvan Csomortani 0f7a3b953a scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface 2019-06-29 06:53:51 +03:00
Istvan Csomortani 04ce10a570 cosmetics: Change Altera to Intel in comments 2019-06-29 06:53:51 +03:00
Istvan Csomortani 2f0dbe6151 intel_mem_asym: Rename the alt_mem_asym to intel_mem_asym 2019-06-29 06:53:51 +03:00
Istvan Csomortani 1e074726db intel_serde: Rename alt_serdes to intel_serdes 2019-06-29 06:53:51 +03:00