Redesign the axi_dacfifo, to increase the supported datarates.
Major modifications:
+ The FIFO consist of two module: WRITE and READ. The axi_dacfifo_dac
was deprecated.
+ Both the AXI write and AXI read transaction are controlled by two
FSM, to increase redability of the code.
+ Support all the possible burst lengths [0..225], handles the last
fractional burst on both sides correctly.
+ Common reset architecture throughout the design, all the internal
registers and memories are reset on the posedge of dma_xfer_req
+ Delete all Altera related sources, for Altera projects
avl_dacfifo should be used.
WIP: foobar
[WIP]axi_dacfifo: Update
axi_dacfifo: Few minor updates, almost working state
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
Laszlo Nagy
Istvan Csomortani