Commit Graph

199 Commits (baf8ec09a3be094c0d508d92303afc084c8b92af)

Author SHA1 Message Date
Istvan Csomortani a2ee478027 axi_ad9361: Fix incorrect merge
Fix paramter propegation for DAC_CLK_EDGE_SEL
2017-10-03 10:51:35 +01:00
Istvan Csomortani 49293f7a87 axi_ad9361: Fix the last incorrect merge
The last merge broke a couple of source files of this core. This
commit brings all the core to a functional state.
2017-10-03 09:15:23 +01:00
Istvan Csomortani 89bd8b44d4 Merge branch 'dev' into hdl_2017_r1 2017-09-26 07:42:19 +01:00
Rejeesh Kutty 1c386d4d34 hdlmake.pl- updates 2017-08-07 16:09:20 -04:00
Istvan Csomortani 420245337d axi_ad9361: Update constraint file
Timing constraints, related to the PPS receiver, should be applied just
when the module is instantiated into the core.
2017-08-04 16:20:33 +01:00
Istvan Csomortani 7cdb11cc34 axi_ad9361: Update the PPS receiver module
+ Add a HDL parameter for the PPS receiver module :
PPS_RECEIVER_ENABLE. By default the module is disabled.
  + Add the CMOS_OR_LVDS_N and PPS_RECEIVER_ENABLE into the CONFIG
register
  + Define a pps_status read only register, which will be asserted, if the free
running counter reach a certain fixed threshold. (2^28) The register can
be deasserted by an incomming PPS only.
2017-08-02 16:38:23 +01:00
Lars-Peter Clausen de4fe30238 library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size
The external s_axi_{awaddr,araddr} signals that are connect to the core
have their width set according to the specified size of the register map.

If the s_axi_{awaddr,araddr} signal of the core is wider (as it currently
is for many cores) the MSBs of those signals are left unconnected, which
generates a warning.

To avoid this make sure that the signal width matches the declared register
map size.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 15:21:25 +02:00
Rejeesh Kutty c1e990b575 ad9361/sw- current sw requires clock edge swap 2017-07-31 14:48:25 -04:00
Rejeesh Kutty 4faa622f43 library/ad9361- gps_pps default value 2017-07-31 09:14:45 -04:00
Rejeesh Kutty adcd092ba3 library/ad9361- add pps module 2017-07-31 09:06:50 -04:00
Rejeesh Kutty 9f9955a84c hdlmake.pl updates 2017-07-31 09:02:12 -04:00
Lars-Peter Clausen d7e87a60a9 Remove executable flag from non-executable files
All of these files are source code and are not executable standalone.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 17:56:07 +02:00
Adrian Costina 289b170dfd axi_ad9361: Fix altera lvds interface, reverting to an older working version 2017-07-28 10:09:17 +01:00
Istvan Csomortani 8ffc35735a axi_ad9361: ad_pps_receiver integration
The ad_pps_receiver is instantiated at the top of core.
The rcounter is placed into adc/dac_common registers space, at the
address 0x30 (word aligned).
The interrupt mask is placed into adc/dac_common, at the address 0x04
(word aligned). Because the core has an instance of both modules, the
interrupt masks are OR-ed together.
2017-07-28 07:57:13 +01:00
Rejeesh Kutty f26c1de38a ad9361/xilinx/lvds_if- fix frame check 2017-07-25 16:37:01 -04:00
Rejeesh Kutty 3eeba8273a hdlmake.pl/fmcomms2- updates 2017-07-24 16:33:40 -04:00
Rejeesh Kutty ff50963c7f axi_ad9361- altera/xilinx reconcile- may be broken- do not use 2017-07-24 16:28:50 -04:00
Rejeesh Kutty 206ea1f70a ad9361/xilinx- missing up_rstn 2017-07-24 15:52:00 +01:00
Rejeesh Kutty 247e540cf0 hdl/library- fix syntax errors/synthesis warnings 2017-07-24 15:31:22 +01:00
Rejeesh Kutty bc4526cc8a axi_ad9361/altera- add 10 support 2017-07-21 10:33:44 -04:00
Rejeesh Kutty 9b26763e3b ad9361/xilinx- missing up_rstn 2017-07-21 09:08:28 -04:00
Rejeesh Kutty d132ed45cd arradio- timing violations fix 2017-07-20 15:08:21 -04:00
Rejeesh Kutty 6c986d9b6a hdl/library- fix syntax errors/synthesis warnings 2017-07-20 14:07:32 -04:00
Rejeesh Kutty a63e268d6e arradio/c5soc- interface updates 2017-07-20 13:05:07 -04:00
Rejeesh Kutty fca88caf93 arradio/c5soc- interface updates 2017-07-20 13:05:07 -04:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Rejeesh Kutty ff037c0286 altera 16.1 ip changes 2017-05-26 10:48:00 -04:00
Rejeesh Kutty 097924b95d altera 16.1 ip changes 2017-05-26 10:46:28 -04:00
Istvan Csomortani 10898d6618 constraints: Split the regmap CDC constraint into separate file 2017-05-25 15:12:16 +03:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Rejeesh Kutty c728299e71 altera- default to latest version 2017-05-12 13:25:17 -04:00
AndreiGrozav e4ae391237 axi adc cores: Add missing ports to up_adc_common instance 2017-05-12 13:39:05 +03:00
AndreiGrozav 0e1e507541 axi dac cores: Add missing ports to up_dac_common instance 2017-05-12 13:37:34 +03:00
Rejeesh Kutty fea6eb68be up_adc_common- port name changes 2017-05-10 14:45:17 -04:00
Istvan Csomortani 85a647eda8 axi_ad9361: Fix ad_cmos_out instantiations
This is a patch for 3627b89
2017-04-26 10:39:54 +03:00
Istvan Csomortani 52305f74c8 altera/ad_cmos_in|out: Delete redundant parameter 2017-04-25 12:06:33 +03:00
Istvan Csomortani 3627b892c3 xilinx/ad_cmos_in|out: Delete redundant parameter
The LVCMOS standard is a single ended IO standard. The SINGLE_ENDED
parameter is redundant in this case.
2017-04-25 11:02:35 +03:00
Istvan Csomortani db0cd63ed3 axi_ad9361: Fix Warning[Synth 8-2611]
In Verilog-2001 standard, redeclaration of an output port as a wire
is not allowed.
2017-04-19 13:52:13 +03:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
Istvan Csomortani c1bdfca4c3 library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
Istvan Csomortani c46989e4e8 Makefile: Update Makefiles for libraries 2017-03-30 18:33:22 +03:00
Istvan Csomortani 31a5c674f2 fmcomms2: Update constraints file paths 2017-03-30 16:16:02 +03:00
Istvan Csomortani ea7e93d27f fmcomms2: Use the new constriants from 335fef0 2017-03-29 18:36:09 +03:00
Rejeesh Kutty 1ef064ac03 axi_ad9361- add receive init delay 2017-03-13 16:28:38 -04:00
Rejeesh Kutty 0ae79ca7ac move/rename - delay script belongs to ad9361 2017-03-10 12:44:32 -05:00
Istvan Csomortani 6b90054343 axi_ad9361: Define CDC constraint for tdd_sync 2017-02-24 11:24:07 +02:00
Istvan Csomortani 94bda1d415 axi_ad9361: Preserve 1bit CDCs with ASYNC_REG true 2017-02-23 11:43:10 +02:00
Istvan Csomortani 2b354af876 axi_ad9361_tdd: Register the tdd_sync_cntr output 2017-02-23 11:31:23 +02:00
Adrian Costina 8ebc8fe4e2 updated makefiles 2016-12-09 23:06:41 +02:00