3 Commits (bb0021a9260f5b8ec67b912e744eb1e0aef51385)

Author	SHA1	Message	Date
Istvan Csomortani	1c23cf4621	all: Update verilog files to verilog-2001	2017-04-13 11:59:55 +03:00
Istvan Csomortani	29a0f27cd1	ad_edge_detect: Add a flop to output, reset is active high	2015-12-14 15:40:29 +02:00
Istvan Csomortani	d6eae81bc1	axi_ad7616: Add the control module to the core, finish up SPI integration	2015-11-13 18:14:21 +02:00