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59 Commits (bc5974d789d2b3f34d3b0b3b0f37782442529f57)

Author SHA1 Message Date
Dan Hotoleanu 77f3e5155b ad9081_fmca_ebz: Fix signal length parameter 
Corrected the length parameter for the rx_data input.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
 2021-12-08 14:29:48 +02:00
Laszlo Nagy 80b3fc2d0a ad9081_fmca_ebz: versal: Remove unused GT reset input pin 
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
 2021-11-22 16:18:29 +02:00
Laszlo Nagy 1ec0993d33 ad9081_fmca_ebz/vcu128: Remove ref clock replica 
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
 2021-11-22 16:18:29 +02:00
Laszlo Nagy e76f287e73 ad9081_fmca_ebz:vcu128: Initial version 
* 4Txs / 4Rxs per MxFE
 * Tx I/Q Rate: 250 MSPS
 * Rx I/Q Rate: 250 MSPS
 * DAC JESD204B: Mode 9, L=4, M=8, N=N'=16
 * ADC JESD204B: Mode 10, L=4, M=8, N=N'=16
 * DAC-Side JESD204B Lane Rate: 10Gbps
 * ADC-Side JESD204B Lane Rate: 10Gbps
 2021-11-19 18:08:16 +02:00
Laszlo Nagy e00def31d0 ad9081_fmca_ebz: versal: Remove external gt_reset logic 2021-11-19 14:01:48 +02:00
Laszlo Nagy 0b9631f1f7 ad9081_fmca_ebz: versal: Rename nets 2021-11-19 14:01:48 +02:00
Laszlo Nagy ca6248ba88 ad9081_fmca_ebz/common/versal_transceiver.tcl: Reset also PLL 2021-11-19 14:01:48 +02:00
Laszlo Nagy 731ed0a7a5 ad9081_fmca_ebz/vck190: Updated to hierarchical versal transceiver 
Vivado cannot nest multiple block designs than two layers. This makes
replication of designs difficult.

Create a hierarchy around the Versal transceiver that includes also the
converters, this type of interface would match the util_adxcvr
interface.

Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
 2021-11-19 14:01:48 +02:00
Laszlo Nagy 1d951cfbae ad9081_fmca_ebz/vck190: Change default profile to 2 lanes 2021-11-19 14:01:48 +02:00
stefan.raus adad6c930d ad9081_fmca_ebz_qsys.tcl: Add RX_LANE_RATE and TX_LANE_RATE parameters 
For ad9081/a10soc project, the RX_LANE_RATE and TX_LANE_RATE were computed
from SAMPLE_RATE. Remove SAMPLE_RATE and add RX_LANE_RATE and TX_LANE_RATE
as parameters. Update also computation examples from comments.

Signed-off-by: stefan.raus <stefan.raus@analog.com>
 2021-11-12 13:04:57 +02:00
Robin Getz 63b6711cfa start adding some doc to the ./projects directory 
This adds a Readme.md to each project directory with pointers to project
documentation in the wiki, and the drivers (if they exist). This will
help with some autogenerated doc in the wiki, that is generated with the
innovatily named "wiki_summary.sh" shell script that parses through
these Readme.md files, and generates a summary table.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Iacob Liviu Mihai <liviu.iacob@analog.com>
 2021-11-10 14:01:06 +02:00
Filip Gherman 9295218a64 projects/ad9081_fmca_ebz: Updated makefiles 2021-10-05 16:56:57 +03:00
Laszlo Nagy 51b643b978 Makefile: Fix misc makefiles from projects and library 2021-10-05 14:24:48 +03:00
Laszlo Nagy 3a1babe366 ad9081_fmca_ebz/vck190: Reset GT with HMC7044 lock 
Reset transceiver with a pulse
 2021-10-05 14:09:51 +03:00
Laszlo Nagy 2562aead32 ad9081_fmca_ebz/common: Drive Rx DMA system side with DMA clock 2021-10-05 14:09:51 +03:00
Laszlo Nagy 8d547f31e1 ad9081_fmca_ebz/vck190: Initial version 2021-10-05 14:09:51 +03:00
Laszlo Nagy 6c58a8d1ab ad9081_fmca_ebz/common: Add Versal transceiver support 2021-10-05 14:09:51 +03:00
David Winter edd2956d58 data_offload: Fix util_[cu]pack offset to TDD syncs 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-09-30 14:45:54 +03:00
David Winter b9554a9a5a ad9081_fmca_ebz: Integrate axi_tdd into zcu102 design 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-09-30 14:45:54 +03:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
David Winter e9e278c898 ad9081_fmca_ebz: Remove bypass gpio 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-08-06 11:55:24 +03:00
David Winter 2178191610 ad9081_fmca_ebz: Switch util_dacfifo to data_offload engine 
Memory requirements are the same as with the dacfifo (1 MiB).

Signed-off-by: David Winter <david.winter@analog.com>
 2021-08-06 11:55:24 +03:00
Laszlo Nagy 75b965e87f ad9081_fmca_ebz/zcu102: Enable 204C modes 2021-06-10 09:53:43 +03:00
Laszlo Nagy 27465ce9c0 ad9081_fmca_ebz/zcu102: Fix spaces 2021-06-10 09:53:43 +03:00
Laszlo Nagy 0ad691a603 ad9081_fmca_ebz/zcu102: Differentiate parameters based on lane rate 2021-05-14 15:39:40 +03:00
Laszlo Nagy 8183599b51 ad9081_fmca_ebz/zcu102: Fix typo 2021-05-14 15:39:40 +03:00
Laszlo Nagy cf7f45ffcc ad9081_fmca_ebz: Fix for F=8 2021-05-14 15:39:40 +03:00
Laszlo Nagy 7b2ba41bdd ad9081_fmca_ebz/vcu118: Adjust QPLL params and diff swing 
This commit fixes the 16.5Gbps lane rate case where the link drops
after few seconds an initial successful link up happens.
A few seconds delayed calibration process can workaround this but with
having the differential drivers swing increased this is no longer
required.
 2021-05-14 15:39:40 +03:00
Laszlo Nagy 0d9e38bdbe ad9081_fmca_ebz: Update path to common block design 
Use absolute paths so ad9082 wrapper project can include the
system_bd.tcl instead of duplicating code.
 2021-05-14 15:39:40 +03:00
Laszlo Nagy 680d28476c ad9081_fmca_ebz: Add LANE_RATE param to all projects 
The block design expects a lane rate to be set in the system project.
 2021-05-14 15:39:40 +03:00
Laszlo Nagy bd6ec360e2 ad9081_fmca_ebz/vcu118: Set XCVR params for 204C link 
Set XCVR parameter for 204C 24.75 Gbps with a  dynamic range of 10Gbps..24.75Gpbs

Organize XCVR params based on lane rate
 2021-05-14 15:39:40 +03:00
Laszlo Nagy 693c002668 ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd: Add 204C support for XCVR 
Remove Xilinx PHY and simplify project
 2021-05-14 15:39:40 +03:00
Laszlo Nagy d92f925b06 ad9081_fmca_ebz: Disable XBAR from DAC TPL 2021-05-14 15:39:40 +03:00
stefan.raus 4a772265a9 Update Quartus Prime version from 19.3.0 to 20.1.0 
adi_project_intel.tcl: Change quartus version to 20.1.0.
library: Set qsys version so that IP instances won't require a specific version.
 2021-03-08 11:29:33 +02:00
Laszlo Nagy 6b13b32f24 ad9081_fmca_ebz: Workaround DMA bug when bus size equals max burst size 2021-03-04 11:13:29 +02:00
Laszlo Nagy 0374a7c1ac ad9081_fmca_ebz/vcu118: Added common 204C use cases as example 2021-02-05 15:24:15 +02:00
Laszlo Nagy ddd8a14790 ad9081_fmca_ebz: Remove system reset from Xilinx PHY 
Reset in device clock domain caused timing failures.
Since link reconfiguration is not supported the reset is not required.
 2021-02-05 15:24:15 +02:00
Laszlo Nagy af3e1c7003 ad9081_fmca_ebz/a10soc: Np 12 support 2021-02-05 15:24:15 +02:00
Laszlo Nagy bb9eafceef ad9081_fmca_ebz/zcu102: Add case analysis to select correct out clock frequency 2021-02-05 15:24:15 +02:00
Laszlo Nagy d0f8a81b2f ad9081_fmca_ebz: Np 12 support 
204B functional
204C functional
 2021-02-05 15:24:15 +02:00
Laszlo Nagy 0fd5590e56 ad9081_fmca_ebz: a10soc: Initial version 
Parametrizable project with default profile of:

  M=8 L=4 SampleRate=250 MSPS
  LaneRate=10 Gbps
 2021-02-05 10:24:59 +02:00
Sergiu Arpadi 6f2f2b8626 makefile: Regenerate make files 2021-01-20 01:02:56 +02:00
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a 
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
 2021-01-20 01:02:56 +02:00
Laszlo Nagy da9828a63e ad9081:zcu102: Expose parameters to environment 
Allow setting project parameters from the environment.
 2021-01-19 17:10:08 +02:00
Laszlo Nagy 3dd370a27c ad9081_fmca_ebz: enable xbar in DAC TPL 2020-11-27 09:45:11 +02:00
Laszlo Nagy ad755788a0 ad9081_fmca_ebz/zc706: Initial version 
M=8 L=4 SampleRate=250 MSPS
LaneRate=10 Gbps
 2020-11-12 15:46:27 +02:00
Laszlo Nagy e9f319e3d7 ad9081_fmca_ebz: HP0 is already initialized in ZC706 
On carriers like ZC706 the HP0 interconnect is in already in use so it must
not be initialized here.
 2020-11-12 15:46:27 +02:00
Adrian Costina 9093a8c428 library: Move ad_iobuf to the common library, as it's not Xilinx specific 
Updated all system_project and Makefiles
 2020-11-02 16:13:35 +02:00
Laszlo Nagy 4026eaa19b ad9081_fmca_ebz: Fix device clocks termination 
The device clocks are AC coupled LVDS lines without external termination.
For proper operation internal differential termination must be enabled,
the DQS_BIAS will DC bias the AC coupled signal to VCCO/2 (1.8/2) 0.9V
 2020-10-06 16:13:21 +03:00
Sergiu Arpadi d8ab27b2af sysid: Remove cstring init string 2020-09-30 19:12:24 +03:00