3 Commits (bdd7e29bae6fe111c64386ce07aa11caf7b40923)

Author	SHA1	Message	Date
AndreiGrozav	03e744f0f1	daq1_zed: Lower the adc and daq clock to 450MHz ... The FPGA fabric on zedboard is a -1 speadgrade (max bufg clk 464MHz)	2017-10-04 13:01:14 +01:00
Rejeesh Kutty	9f9955a84c	hdlmake.pl updates	2017-07-31 09:02:12 -04:00
AndreiGrozav	6b897dabe5	daq1_zed: Initial commit	2017-07-31 14:26:23 +03:00