12fc6d1672
axi_dmac: Indicate that the core does not issue narrow AXI bursts
...
The axi_dmac core does not issue narrow AXI bursts. Indicate this by
setting the SUPPORTS_NARROW_BURST property to 0 on both AXI master
interfaces.
This allows connected slaves to know that they will not receive narrow
bursts, which allows them to disable support for it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:18 +02:00
5f307f862f
axi_dmac: Use sane defaults for the AXI protocol type
...
The axi_dmac core generates requests which are both AXI3 and AXI4
compliant. This means it is possible to connect it to both a AXI3 or AXI4
slave port without needing a AXI protocol converter. Unfortunately it is
not possible to declare a port as both AXI3 and AXI4 compliant, so the core
has the C_DMA_AXI_PROTCOL_SRC and C_DMA_AXI_PROTOCOL_DEST parameters, which
allow to configure the protocol type of the corresponding AXI master
interface. Currently the default is always AXI4.
But when being used on ZYNQ it is most likely that the AXI master interface
of the DMAC core ends up being connected to the AXI3, so change the default
to AXI3 if the core is instantiated in a ZYNQ design.
The default can still be overwritten by explicitly setting the
configuration property.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:17 +02:00
f079b2193a
axi_dmac: Add support for auto-detecting asynchronous clock configuration
...
Add support for querying the clock domains of the clock pins for the
axi_dmac controller. This allows the core to automatically figure out
whether its different parts run in different clock domains or not and setup
the configuration parameters accordingly.
Being able to auto-detect those configuration parameters makes the core
easier to use and also avoids accidental misconfiguration.
It is still possible to automatically overwrite the configuration
parameters by hand if necessary.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:15 +02:00
19f7d8500c
adi_ip.tcl: Add support for adding bd files to a core
...
bd files can be used to automate certain tasks in IP integrator when the
core is instantiated. Add a helper command for adding such files to a core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:14 +02:00
39320ef48b
axi_dmac: Fix source pause signal
...
For the source controller use the pause signal that has been properly
transferred to the source clock domain rather than the pause signal from
the request clock domain.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:13 +02:00
91bb54467b
axi_dmac: Generate per core instance constraint file
...
When having multiple DMA cores sharing the same constraint file Vivado
seems to apply the constraints from the first core to all the other cores
when re-running synthesis and implementation from within the Vivado GUI.
This causes wrong timing constraints if the DMA cores have different
configurations. To avoid this issue use a TTCL template that generates a
custom constraint file for each DMA core instance.
This also allows us to drop the asynchronous clock detection hack from the
constraint file and move it to the template and only generate the CDC
constraints if the clock domains are asynchronous.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:12 +02:00
0f5f21eec2
adi_ip.tcl: Add helper function to add TTCL files to a core
...
Add a helper function which allows to add TTCL templates files to a core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:10 +02:00
46808c4c41
util_wfifo: Changed some reset for several registers from asynchronous to synchronous for better integration with the FIFO
2015-09-16 18:55:47 +03:00
6804f3377a
axi_ad9643: Updated core with latest constraints
2015-09-16 15:49:13 +03:00
5347c058df
axi_ad9122: Updated core with latest constraints
2015-09-16 15:48:33 +03:00
884f45c81d
common library: Registered dc_filter and iq_correction coefficients
2015-09-16 14:24:18 +03:00
052860cbc3
axi_dmac: Fix source pause signal
...
For the source controller use the pause signal that has been properly
transferred to the source clock domain rather than the pause signal from
the request clock domain.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-16 11:02:08 +02:00
5af371db6b
axi_dmac: Generate per core instance constraint file
...
When having multiple DMA cores sharing the same constraint file Vivado
seems to apply the constraints from the first core to all the other cores
when re-running synthesis and implementation from within the Vivado GUI.
This causes wrong timing constraints if the DMA cores have different
configurations. To avoid this issue use a TTCL template that generates a
custom constraint file for each DMA core instance.
This also allows us to drop the asynchronous clock detection hack from the
constraint file and move it to the template and only generate the CDC
constraints if the clock domains are asynchronous.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-15 19:54:33 +02:00
522f30ce21
adi_ip.tcl: Add helper function to add TTCL files to a core
...
Add a helper function which allows to add TTCL templates files to a core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-15 19:00:56 +02:00
7c896ba5f8
axi_ad9361: Fixed constraints definition
2015-09-14 18:20:30 +03:00
67ffeb18e8
axi_ad9739a: Updated core with latest constraints
2015-09-11 14:04:33 +03:00
e33403816c
axi_ad9265: Updated core with latest constraints
2015-09-11 11:26:28 +03:00
5bc16159fa
ad_tdd_sync: The resync will reset all the control lines
2015-09-10 11:28:36 +03:00
a679251d7d
Makefiles: Update Make
2015-09-09 17:13:19 +03:00
85ffc25ec5
ad_tdd_sync: Update the synchronization logic
...
The synchronization interface is a single bidirectional line. Output for Master, input for Slave.
The sync_period value is relative to frame length and the digital interface clock. The actual synchronization
period will be: sync_period * frame_length * fb_clock_cycle
2015-09-09 12:31:58 +03:00
5a566b9e5d
ad_tdd_control: Add delay compensation for the control lines
2015-09-09 12:24:26 +03:00
6acb350ee5
axi_dmac: Update for axi_dmac_constr.xdc
...
Parameter called 'processing_order' default value is 'late'. No need to specify it at process call.
2015-09-09 12:08:35 +03:00
381ffd43c1
gtlb- remove pn test-reset
2015-09-08 13:52:33 -04:00
9bef9742b7
jesd_gt- cosmetic changes
2015-09-03 16:16:24 -04:00
84ced344d9
gtlb- up-sync make w1c
2015-09-03 16:16:22 -04:00
e0b5044aa3
axi_dmac: Disable dummy AXI ports for Xilinx IPI
...
The memory mapped AXI interfaces for the AXI-DMAC are uni-directional.
Which means they are either write-only or read-only. Unfortunately the
Altera tools can't handle this, so we had to add dummy signals for the
other direction.
The Xilinx tools on the other hand handle uni-directional AXI interfaces
and in fact IPI can do a better job and use less resources when creating
the AXI interconnects when it knows that the interface is uni-directional.
So always disable the dummy ports for the IPI package.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
2a09257f38
pzslb- updates - wip
2015-08-31 15:41:28 -04:00
c1b01517f8
util_gtlb: added
2015-08-31 15:41:22 -04:00
1e5afdd535
axi_hdmi_tx- altera ip changes
2015-08-28 13:48:33 -04:00
6cf7eb5ad4
axi_hdmi_tx- altera ip changes
2015-08-28 13:48:33 -04:00
4554eb03b0
axi_hdmi_tx- altera ip changes
2015-08-28 13:48:33 -04:00
704385a8dc
axi_hdmi_tx- altera ip changes
2015-08-28 13:48:33 -04:00
a33c08725b
axi_hdmi_tx- altera ip changes
2015-08-28 13:48:33 -04:00
1cd3435147
up_delay_cntrl- cosmetics
2015-08-28 13:16:18 -04:00
8fddf983d2
up_hdmi_tx- common/generic instance names
2015-08-27 13:17:06 -04:00
88f806f584
ad9361- alt io matching
2015-08-27 11:55:24 -04:00
74e72021f7
ad9361- ensm through dev-if
2015-08-27 11:41:53 -04:00
664ef017bb
ad9361- ensm through dev-if
2015-08-27 11:41:52 -04:00
29b0ec0378
ad9361- ensm through dev-if
2015-08-27 11:41:51 -04:00
d82d37c23f
ad9361- ensm through dev-if
2015-08-27 11:41:49 -04:00
2259b6cbf7
ad9361- ensm through dev-if
2015-08-27 11:41:48 -04:00
20ee10ea46
common/ad_lvds_out- add single ended
2015-08-27 11:41:47 -04:00
c56b534ec0
dacfifo- remove interfaces
2015-08-27 11:18:00 -04:00
ba64de228e
ip-constr- register name changes
2015-08-27 11:18:00 -04:00
f3410a7db1
xpack- remove useless interfaces
2015-08-26 14:12:14 -04:00
b0d22d323a
ad9361- axi-clock definitions
2015-08-26 14:11:43 -04:00
4655af7bf6
2015.2 updates
2015-08-26 11:33:44 -04:00
18f688514b
2015.2 updates
2015-08-26 11:33:37 -04:00
7780b3a3a2
2015.2 updates
2015-08-26 11:33:27 -04:00
7b858bc5ad
Revert commit 6b99ce
...
Revert 6b99ce2482
2015-08-26 13:48:28 +03:00
386cc74ab4
util_axis_fifo: Fix port names at util_axis_fifo_ip.tcl
...
Fix port names at the 'port_maps' attribute of the adi_add_bus process call.
2015-08-25 09:41:34 +03:00
c2ea667a01
library/IPI: Set ASSOCIATED_RESET parameter for AXI interface
...
For some reason, if a core has an AXI and an AXI Stream interface too, the tool sets the AXI interface's ASSOCIATED_RESET parameter to the AXI Stream interface's reset.
This cause an unconnected AXI reset port in the block design. This 'set_property' command intended to overwrite this automated setup.
2015-08-25 09:36:42 +03:00
0c3f110bff
library: Fix broken parameters
...
Fix the broken parameters for the following IP cores: axi_i2s_adi, axi_spdif_tx, util_cpack. Make additional name changes on the local parameters.
2015-08-25 09:19:47 +03:00
da315eb6c0
library: 2015.2 updates
...
IPI bus interface names have changed in this new release.
2015-08-25 09:13:24 +03:00
0077117f94
dac/adc- make common instances
2015-08-21 14:41:39 -04:00
c45d39df51
dac/adc- make common instances
2015-08-21 14:41:35 -04:00
e3ec6b48fc
dac/adc- make common instances
2015-08-21 14:41:30 -04:00
f31c1c9caa
dac/adc- make common instances
2015-08-21 14:41:26 -04:00
e4e4700950
dac/adc- make common instances
2015-08-21 14:41:13 -04:00
54b4365f6c
dac/adc- make common instances
2015-08-21 14:41:09 -04:00
799001403f
mult-macro: use primitive parameters
2015-08-20 13:54:16 -04:00
111287604b
xcvr- remove status constraint
2015-08-20 13:54:15 -04:00
0d482e7ef6
axi_dmac: Disable dummy AXI ports for Xilinx IPI
...
The memory mapped AXI interfaces for the AXI-DMAC are uni-directional.
Which means they are either write-only or read-only. Unfortunately the
Altera tools can't handle this, so we had to add dummy signals for the
other direction.
The Xilinx tools on the other hand handle uni-directional AXI interfaces
and in fact IPI can do a better job and use less resources when creating
the AXI interconnects when it knows that the interface is uni-directional.
So always disable the dummy ports for the IPI package.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-08-20 18:25:01 +02:00
37c14e782d
axi_dmac: Disable dummy AXI ports for Xilinx IPI
...
The memory mapped AXI interfaces for the AXI-DMAC are uni-directional.
Which means they are either write-only or read-only. Unfortunately the
Altera tools can't handle this, so we had to add dummy signals for the
other direction.
The Xilinx tools on the other hand handle uni-directional AXI interfaces
and in fact IPI can do a better job and use less resources when creating
the AXI interconnects when it knows that the interface is uni-directional.
So always disable the dummy ports for the IPI package.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-08-20 18:12:10 +02:00
d59ec3b36d
unused ip cores
2015-08-20 11:37:16 -04:00
b0079e60bf
ad-rst - common instance for adc/dac
2015-08-20 11:37:16 -04:00
d67a4a3088
axi_ad9434: Removed duplicate parameter
2015-08-20 18:19:59 +03:00
6b99ce2482
library: Added common constraints for all cores. Commented code that needs to be updated to 2015.2
2015-08-20 18:17:38 +03:00
6ae0c8f85e
library: Fixed changes related to parameters
2015-08-20 18:13:54 +03:00
0d1d8310fd
axi_dmac: Parameter changes
...
Update parameters on inc_id.h and axi_dmac_ip.tcl
2015-08-20 16:06:26 +03:00
82e703df23
parameter changes
2015-08-20 08:53:51 -04:00
db18924f8a
library/scripts: Fix ipx::get_file_groups process call
...
ipx::get_file_groups does not work, if there is specified just a [<pattern>] for its argument. Need to use a -filter to get proper result.
2015-08-20 10:56:37 +03:00
0dfb3e2019
tcl_scripts: Update Vivado version number to 2015.2.1
2015-08-20 10:50:52 +03:00
d52308f074
axi_dmac: Change parameter name 2D_TRANSFER
...
Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 10:14:22 +03:00
6ab28ccb0c
axi-jesd-xcvr- parameter changes
2015-08-19 14:55:11 -04:00
28eb09b4d5
axi-jesd-xcvr- parameter changes
2015-08-19 14:55:08 -04:00
928ee4972b
dac/adc-rst: common ad-rst instance
2015-08-19 14:54:43 -04:00
483e375910
dac/adc-rst: common ad-rst instance
2015-08-19 14:54:38 -04:00
5e252f17b9
cpack- ad_rst port addition
2015-08-19 13:26:38 -04:00
f8b3346e97
axi_jesd_xcvr- ad_rst register changes
2015-08-19 13:26:38 -04:00
f7f902c7b4
axi_jesd_xcvr- ad_rst register changes
2015-08-19 13:26:38 -04:00
57cfb7cfb1
hdl/library: Update the IP parameters
...
The following IP parameters were renamed:
PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
549801cf2e
library: Delete unused IP cores
...
Delete IP "controllerperipheralhdladi_pcore" and "ip_pid_controller"
2015-08-19 12:24:10 +03:00
10d9de39a1
axi_ad9361/tdd: Update the synchronization logic
...
The master will regenerate a sync pulse periodically. The period can be defined by software.
2015-08-19 12:21:23 +03:00
bcee3e04d4
fmcomms2_tdd: Update tdd_enabaled path
...
This line controls the mux, which switch between hdl and software (GPIO) control of the ENABLE/TXNRX pins.
Fix the broken path and change the name from "tdd_enable" to "tdd_enabled".
2015-08-19 12:14:05 +03:00
8e536ad8d1
axi_ad9361: Update Make file
2015-08-19 12:14:03 +03:00
e64baad54a
axi_dmac: Fix a bug occuring on transfers < one beat
...
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2015-08-19 10:23:26 +02:00
114d48d4e1
axi_dmac: Fix a bug occuring on transfers < one beat
...
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2015-08-19 10:23:06 +02:00
f5de5ca487
usdrx1: Fixed jesd core parameters. Fixed synchronization mechanism
2015-08-19 10:12:24 +03:00
b84afcdcd1
Merge branch 'master' into dev
...
Conflicts:
library/Makefile
library/axi_ad6676/axi_ad6676_ip.tcl
library/axi_ad9122/axi_ad9122_core.v
library/axi_ad9122/axi_ad9122_ip.tcl
library/axi_ad9144/axi_ad9144_ip.tcl
library/axi_ad9152/axi_ad9152_ip.tcl
library/axi_ad9234/axi_ad9234_ip.tcl
library/axi_ad9250/axi_ad9250_hw.tcl
library/axi_ad9250/axi_ad9250_ip.tcl
library/axi_ad9361/axi_ad9361.v
library/axi_ad9361/axi_ad9361_dev_if_alt.v
library/axi_ad9361/axi_ad9361_ip.tcl
library/axi_ad9361/axi_ad9361_rx_channel.v
library/axi_ad9361/axi_ad9361_tdd.v
library/axi_ad9361/axi_ad9361_tx_channel.v
library/axi_ad9625/axi_ad9625_ip.tcl
library/axi_ad9643/axi_ad9643_channel.v
library/axi_ad9643/axi_ad9643_ip.tcl
library/axi_ad9652/axi_ad9652_channel.v
library/axi_ad9652/axi_ad9652_ip.tcl
library/axi_ad9671/axi_ad9671_constr.xdc
library/axi_ad9671/axi_ad9671_ip.tcl
library/axi_ad9680/axi_ad9680_ip.tcl
library/axi_ad9739a/axi_ad9739a_ip.tcl
library/axi_dmac/axi_dmac_constr.sdc
library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl
library/axi_jesd_gt/axi_jesd_gt_constr.xdc
library/axi_jesd_gt/axi_jesd_gt_ip.tcl
library/axi_mc_speed/axi_mc_speed_constr.xdc
library/common/ad_gt_channel_1.v
library/common/ad_gt_common_1.v
library/common/ad_gt_es.v
library/common/ad_iqcor.v
library/common/ad_jesd_align.v
library/common/ad_rst.v
library/common/altera/ad_xcvr_rx_rst.v
library/common/up_adc_common.v
library/common/up_axis_dma_rx.v
library/common/up_axis_dma_tx.v
library/common/up_clkgen.v
library/common/up_clock_mon.v
library/common/up_dac_common.v
library/common/up_gt.v
library/common/up_hdmi_tx.v
library/common/up_tdd_cntrl.v
library/common/up_xfer_cntrl.v
library/common/up_xfer_status.v
library/util_cpack/util_cpack.v
library/util_cpack/util_cpack_ip.tcl
library/util_dac_unpack/util_dac_unpack_hw.tcl
library/util_jesd_align/util_jesd_align.v
library/util_jesd_xmit/util_jesd_xmit.v
library/util_upack/util_upack_ip.tcl
library/util_wfifo/util_wfifo.v
library/util_wfifo/util_wfifo_constr.xdc
library/util_wfifo/util_wfifo_ip.tcl
projects/arradio/c5soc/system_bd.qsys
projects/common/vc707/vc707_system_bd.tcl
projects/common/zc706/zc706_system_plddr3.tcl
projects/daq2/a10gx/Makefile
projects/daq2/a10gx/system_bd.qsys
projects/daq3/common/daq3_bd.tcl
projects/daq3/zc706/system_bd.tcl
projects/fmcjesdadc1/a5gt/Makefile
projects/fmcjesdadc1/a5gt/system_bd.qsys
projects/fmcjesdadc1/a5gt/system_constr.sdc
projects/fmcjesdadc1/a5gt/system_top.v
projects/fmcjesdadc1/a5soc/system_bd.qsys
projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
projects/fmcomms1/ac701/system_bd.tcl
projects/fmcomms1/common/fmcomms1_bd.tcl
projects/fmcomms1/kc705/system_bd.tcl
projects/fmcomms1/vc707/system_bd.tcl
projects/fmcomms1/zc702/system_bd.tcl
projects/fmcomms1/zc702/system_top.v
projects/fmcomms1/zc706/system_bd.tcl
projects/fmcomms1/zc706/system_top.v
projects/fmcomms1/zed/system_bd.tcl
projects/fmcomms1/zed/system_top.v
projects/fmcomms2/ac701/system_constr.xdc
projects/fmcomms2/common/fmcomms2_bd.tcl
projects/fmcomms2/kc705/system_constr.xdc
projects/fmcomms2/kc705/system_top.v
projects/fmcomms2/mitx045/system_top.v
projects/fmcomms2/rfsom/system_constr.xdc
projects/fmcomms2/rfsom/system_top.v
projects/fmcomms2/vc707/system_top.v
projects/fmcomms2/zc706/system_bd.tcl
projects/fmcomms2/zc706/system_constr.xdc
projects/fmcomms2/zc706/system_top.v
projects/fmcomms2/zed/system_top.v
projects/imageon/zc706/system_constr.xdc
projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
projects/motcon2_fmc/zed/system_constr.xdc
projects/motcon2_fmc/zed/system_top.v
projects/usdrx1/a5gt/Makefile
projects/usdrx1/a5gt/system_bd.qsys
projects/usdrx1/common/usdrx1_bd.tcl
Conflicts were resolved using 'Mine' (/dev).
2015-08-17 15:15:58 +03:00
c22d1c044b
axi_jesd_gt-- gt interfaces
2015-08-14 15:34:49 -04:00
890f743f1a
util_jesd_gt-- gt interfaces
2015-08-14 15:34:30 -04:00
6eb0b5eeda
scripts-- add interface procedures
2015-08-14 15:33:58 -04:00
2345be2237
interfaces-- transceiver cores
2015-08-14 15:33:36 -04:00
af87b65788
interfaces_ip: added
2015-08-14 11:24:27 -04:00
ebecfde64c
axi_hdmi_tx: common constraints & async resets
2015-08-13 13:03:51 -04:00
a6f6c81795
axi_jesd_gt- gt lane split
2015-08-13 13:03:51 -04:00
041be729f6
common/ip-constrs- uniform simple constraints will do
2015-08-13 13:03:51 -04:00
a2b816beda
common/up_hdmi_tx: wrong clock on vdma status signals
2015-08-13 13:03:51 -04:00
5edf61c40a
ad_rst:- allow preset to be synchronized as reset
2015-08-13 13:03:51 -04:00
2bcac36e33
common/up_- change to asynchronous resets
2015-08-13 13:03:51 -04:00
2b8e1bdb74
adi_ip- parse file list for constraints
2015-08-13 13:03:51 -04:00
3615c9cad7
axi_jesd_gt- bug fixes
2015-08-13 13:03:51 -04:00
44d51e665d
util_jesd_gt- port type fix
2015-08-13 13:03:51 -04:00
8697b0a8d6
axi_jesd_gt- ip script changes
2015-08-13 13:03:51 -04:00
e265ca9ea7
util_jesd_gt- ip tcl changes
2015-08-13 13:03:51 -04:00
a108ca9309
util_jesd_gt- updates
2015-08-13 13:03:51 -04:00
a4076424e0
util_jesd_gt- added
2015-08-13 13:03:51 -04:00
10d4da64dd
axi_jesd_gt: move master/slave control to a util module
2015-08-13 13:03:51 -04:00
3ed350efbc
axi_jesd_gt- split up
2015-08-13 13:03:51 -04:00
e4f94664a6
axi_jesd_gt- remove per lane control/status to channel
2015-08-13 13:03:51 -04:00
f807490ed1
axi_jesd_gt- per lane group
2015-08-13 13:03:51 -04:00
4c8206608c
axi_jesd_gt- separate es-axi
2015-08-13 13:03:51 -04:00
e4b0710923
axi_jesd_gt- per lane split-up
2015-08-13 13:03:51 -04:00
ce26373e8a
axi_ad9671: updated constraints to apply in all cases
2015-08-13 11:53:15 +03:00
0379279bd4
axi_ad9671: Fixed rx_sof pin name
2015-08-12 10:20:09 +03:00
afb9911b6e
Makefiles: Updated makefiles
2015-08-06 19:50:50 +03:00
f59058dd8a
axi_ad9434: Fix the up interface for IO_DELAYs
2015-08-06 15:17:19 +03:00
ad80561379
TDD_regmap: Fix CDC for control signals
2015-08-06 15:16:39 +03:00
e19d476b58
TDD_regmap: Fix addresses
2015-08-06 15:15:50 +03:00
d2c99acae8
fmcomms2/TDD: Update synchronization interface
...
Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 15:14:36 +03:00
6104061d19
axi_ad9434: Fix the up interface for IO_DELAYs
2015-08-04 13:46:15 +03:00
cfc4046821
fmcomms2: Add a synchronization interface for TDD mode.
...
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-29 14:10:56 +03:00
ed6bdf66bd
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic
...
Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-29 11:59:17 +03:00
05ba125694
ad_tdd_control: Connect the reset to all the flops
2015-07-29 11:56:40 +03:00
8e631e56d6
fmcomms2: Add a synchronization interface for TDD mode.
...
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 14:42:54 +03:00
d5d7a24483
util_cpack: Added reset interface
2015-07-28 11:00:54 +03:00
623c3dc333
axi_ad9361: Updated altera core by including tdd related files. Removed deleted ports
2015-07-24 16:41:41 +03:00
caca364c61
ad9652- iqcor iqsel changes
2015-07-24 08:35:13 -04:00
144b8f7383
ad9643- iqcor iqsel changes
2015-07-24 08:34:52 -04:00
43946a54a4
axi_dmac: Added C_FIFO_SIZE parameter
2015-07-24 15:30:10 +03:00
649297a0e3
ad_iqcor- changes
2015-07-23 16:20:46 -04:00
cd5ce3349f
iqcor- move i/q sel inside the module
2015-07-23 15:55:45 -04:00
3d1ffe7bd2
util_cpack: Added reset interface
2015-07-23 17:01:53 +03:00
f7d28e0944
axi_dmac: Removed unneded constraints, as FMCJESDADC1 doesn't work correctly with them
2015-07-23 17:01:02 +03:00
41e9a34886
axi_ad9250: Changed Altera interface specification to be compatible with upack
2015-07-23 16:59:57 +03:00
901bcb2c06
dma- constraints modifications
2015-07-22 12:46:06 -04:00
3d7afb8fc5
jesd-xcvr: constraints modifications
2015-07-22 12:46:06 -04:00
6352884398
jesd-xcvr: common align function
2015-07-22 12:46:06 -04:00
a4461545fa
axi-ip: constraints - altera
2015-07-22 12:46:06 -04:00
ac39329046
axi_spdif_rx: Fix the pl330_dma control path
...
- fix pl330_dma control path
- delete unused control_reg bits
- change the port name spdif_rx_i_osc to spdif_rx_i_dbg
- version_reg is read only
2015-07-22 17:59:52 +03:00
559893c0a3
altera- obsolete cores
2015-07-21 11:04:26 -04:00
86dabbe5fc
jesd-align-- xilinx/altera merge
2015-07-21 10:57:00 -04:00
3a4581a8df
axi-xcvr: removed xcvr compoents
2015-07-21 10:56:04 -04:00
264f9ffbfc
ip_alt- avalon/reset definitions
2015-07-21 10:55:13 -04:00
3101045109
qsys- library group
2015-07-17 10:07:15 -04:00
4e99a2cb01
xcvr: remove signal tap
2015-07-16 08:09:56 -04:00
9f7fff2d2f
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic
...
Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 14:10:49 +03:00
31584cf27e
ad9680- qsys needs interface signal name matching
2015-07-15 15:59:51 -04:00
60c344cea6
ad9144- qsys needs interface signal name matching
2015-07-15 15:59:51 -04:00
Lars-Peter Clausen
Adrian Costina
Istvan Csomortani
Rejeesh Kutty
Paul Cercueil