Commit Graph

6 Commits (be0e2809e9b9facc137f74782e6282b0d54796ef)

Author SHA1 Message Date
PIoandan d3be77931b
Update ad469x spi engine (#1181)
* Update ad469x spi engine

I replaced the SPI Engine connections in the ad469x_bd.tcl with the
spi_engine_create procedure found in the spi_engine.tcl script. Through
these changes, a more generic instantiation for the spi_engine can be
achieved. I also created the ad469x_fmc.txt file for generating the
system_constr.xdc file.

Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
2023-10-24 12:44:48 +03:00
Iulia Moldovan 1cac2d82e1 Add copyright and license to .xdc files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 11:03:02 +03:00
laurent-19 2ae09c9808 Check guidelines. Remove redundancies
* Removed empty/commented lines
 * Regenerated Makefiles
 * Removed redundancies adc channels data width
 * Set data width 32-bit: max resolution and CRC header

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-29 15:08:07 +03:00
Sergiu Arpadi 445cca61ef SPI Engine: Update spi_engine.tcl
The SPI Engine cores were named directly inside the script and this
would mean that for multiple SPI Engine instances IPs with the same
name would appear. These updates will introduce the hierarchy name
into the name given to the cores and will therefore allow for
multiple instances of SPI Engine to be added to the same Xilinx
project.

Projects which use spi_engine.tcl will be updated to account for
these changes.
2023-03-29 15:08:07 +03:00
Sergiu Arpadi 6a374ef457 ad469x/zed: Add multicycle path constraint 2021-03-22 13:05:05 +02:00
sergiu arpadi 35e4eb6a7b ad469x: Add reference design for ad469x eval board 2020-10-22 19:17:10 +03:00