Commit Graph

25 Commits (be0e2809e9b9facc137f74782e6282b0d54796ef)

Author SHA1 Message Date
Iulia Moldovan 68461110aa Replace link in license header from master to main
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2024-01-16 16:48:45 +02:00
Iulia Moldovan c9a7d4d927 Add copyright and license to .tcl, .ttcl files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 15:22:26 +03:00
Iulia Moldovan 27bb69b44c Add copyright and license to .sdc files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 10:41:40 +03:00
Iulia Moldovan 28c06d505f Add/edit copyright and license for .v, .sv files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-11 15:17:41 +03:00
Iulia Moldovan db94628cc6 library & projects: Update Makefiles
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-01-27 11:54:05 +02:00
Bogdan Luncan 72313df81f Updated the makefiles to build the projects in subdirectories based on the build parameters.
Running 'make' will build the default project directly in the project folder (like it did before)
Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory.
Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory.
Running 'make clean' will clean the default project only.
Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build.
Running 'make clean-all' will delete all the built configurations and libraries.

Note that the 'JESD' and 'LANE' words from the parameter names are stripped.

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2022-11-14 09:38:42 +02:00
Iacob_Liviu 482f0489a3 scripts: Merge adi_env.tcl into a single file
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
Iulia Moldovan 961ebe0cc2 projects: Update .v files according to guideline
Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
ladace 6525a37375
ad_fmclidar1_ebz:a10soc Fixed problems with SPI communication with AD9094 (#951)
Now CPH and CPOL are set to 1, also the SPI clock is set to 10MHz

Signed-off-by: Liviu Adace <liviu.adace@analog.com>
2022-06-06 13:00:45 +03:00
ladace ab5c344c89
ad_fmclidar1_ebz:a10soc Fixed SPI communication on Arria 10 (#947)
Signed-off-by: Liviu Adace <liviu.adace@analog.com>
2022-05-24 12:44:03 +03:00
Adrian Costina 62dc310794 Revert "intel: Update projects to use ad_iobuf instead of ALT_IOBUF"
This reverts commit a3a610728c.

Quartus doesn't instantiate correctly the buffer
2022-02-09 17:39:29 +02:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
Sergiu Arpadi 6f2f2b8626 makefile: Regenerate make files 2021-01-20 01:02:56 +02:00
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
stefan.raus 685ca91f19 ad_fmclidar1_ebz/a10soc: Fix a typo
Fixing a typo in projects/ad_fmclidar1_ebz/a10soc/system_top.v.
2020-11-05 12:53:50 +02:00
Adrian Costina a3a610728c intel: Update projects to use ad_iobuf instead of ALT_IOBUF 2020-11-02 16:13:35 +02:00
Istvan Csomortani 37254358dd makefile: Regenerate make files 2020-10-20 12:51:10 +03:00
Sergiu Arpadi d8ab27b2af sysid: Remove cstring init string 2020-09-30 19:12:24 +03:00
Sergiu Arpadi 3241924d14 sysid_intel: Added sysid to intel projects 2020-09-11 15:46:06 +03:00
Istvan Csomortani 32eeedb660 makefile: Update makefiles 2020-05-07 08:41:49 +01:00
Istvan Csomortani 522aacf6d8 ad_fmclidar1_ebz/a10soc: Fix AFE's I2C interface
The AFE's I2C interface should be pin-multiplexed to the FPGA. Also, add
a bidirectional IO buffer for the interface, and make sure it has weak
pull-up resistors.
2020-03-17 07:27:49 +00:00
Istvan Csomortani b3e475cb8b ad_fmclidar1_ebz: Update the IO constraints to revB
The IO location of the laser_driver_otw_n was moved from FMC_HPC_LA27_N
to FMC_HPC_LA31 (laser_gpio[12]).
laser_gpio[11:0] assignments were shifted with one bit to MSB, and laser_gpio[0]
got the old location of the laser_driver_otw_n.
2020-01-31 18:47:37 +02:00
Istvan Csomortani 03bec4b49c ad_fmclidar1_ebz: Interchange SYSREF and DEV_CLK ports location
In ZCU102 LA01_CC_P|N are connected to regional clock, but in order to
receive a device clock properly we have to use pin which is connected
to a  global clock buffer. Luckily SYSREF is connected to global clock
pin; swap to port to receive the device clock correctly.

Also, swap the ports in both ZC706 and A10SOC carriers.
2019-10-17 09:59:23 +03:00
Istvan Csomortani 3084a5d9aa ad_fmclidar1_ebz/a10soc: Fix the comment about the carrier re-work
The project is using the FMCA connector of the board. Make sure that all
the carrier re-work is related to the FMCA connector.
2019-10-17 09:58:52 +03:00
Istvan Csomortani 2344778dd8 ad_fmclidar1_ebz/a10soc: Initial commit
Add initial support for Arria 10 SOC carrier.
2019-10-02 15:32:17 +03:00