Commit Graph

8 Commits (be0e2809e9b9facc137f74782e6282b0d54796ef)

Author SHA1 Message Date
Iulia Moldovan c9a7d4d927 Add copyright and license to .tcl, .ttcl files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 15:22:26 +03:00
Sergiu Arpadi bb3027995a sysid: Add sysid support for de10nano
make adv7513

make 0540
2022-08-02 14:15:34 +03:00
PopPaul2021 0d44bfb4dd
axi_hdmi_tx update for: ZedBoard, ZC706, ZC702, de10nano, ADRV9361-Z7035 (#897) 2022-03-29 16:51:21 +03:00
Adrian Costina fbb2a0e1a0 de10nano: Add hps_conv_usb_n signal to stabilize UART lines
Without defining this signal, the UART lines receive garbage data
when no cable is connected to the J4 USB UART port.
The GPIO9 is enabled in the reference base design along with the
4MA CURRENT_STRENGTH constraint on the UART pins
2021-01-13 15:36:45 +02:00
AndreiGrozav e331abedc6 common/de10nano: Cosmetic updates only 2020-12-08 14:38:04 +02:00
AndreiGrozav 8d378c56bf common/de10nano: Full HD 60 FPS support
-change the video memory interfacing from f2h_axi_slave to
f2h_sdram0
- add f2h_sdram1 port as the default interface for converter DMA
- set as default the full HD resolution at 60 FPS (pixel clock 148.5MHz)
- use a second 200MHz(198MHz) clock from the pixel_clk_pll, as DMA source
to destination clock.
2020-12-08 14:38:04 +02:00
Stanca Pop 043ddbaf9f cn0540: Add de10nano reference design 2020-09-15 18:14:23 +03:00
Stanca.Pop fd1c3c7cdd common/de10nano: Add de10nano base design 2020-09-15 18:14:23 +03:00