* Projects: Add missing sysid IP
* Added make parameters for the sysid ip for the projects: ad9209_fmca_ebz/vck190, ad9213_dual_ebz/s10soc and adrv9009/s10soc
Signed-off-by: Pop Ioan Daniel <pop.ioan-daniel@analog.com>
The default address space for a new bridge is 256 Kbytes. Add an
avl_address_width attribute to the ad_cpu_interoconnect porecess to
define other address space sizes if needed.
The avl_peripheral_mm_bridge will have an 128 Kbyte address space from
address 0x0000.
Due to the interface differences between HPS's AXI4 and DMA's AXI4, the
tool will try to automaticaly add some bridges between the two
interface. Unfortunatly it does generate timing issues at the f2sdram0
interface of the HPS instance. By explicitly instantiating an AXI
bridge, these timing issues disappears.
If we have a lot of peripherals connected to the CPU's memory interface,
the generated interconnect can grow to much decreasing the timing
margin.
One solution is to group the peripherals by its interface types and
functions and use bridges to connect them to the memory interface.
This commit adds the possibility to insert an Avalon Memory Mapped
bridge when we create the connection between the peripheral and CPU.
Should be used just with Avalaon Memory Mapped interfaces.
PIoandan
Iulia Moldovan
Adrian Costina
Istvan Csomortani