Also modified the FIFO ports to have the same widths so that in a
future commit the bypass would be available for cases when the
sampling rate won't be the maximum rate or the number of channels
active will be less than maximum number of channels
Switch RX path reset to be controlled by the TPL and use
RX SYSREF as external synchronization for the ADC TPL
Use TX SYSREF for synchornizing the TX DDS
The device clocks are AC coupled LVDS lines without external termination.
For proper operation internal differential termination must be enabled,
the DQS_BIAS will DC bias the AC coupled signal to VCCO/2 (1.8/2) 0.9V
Added reference design for the ad9656 evaluation board coupled with the
zcu102 carrier board. The JESD204 communication link that transfers data
from the 4 ADCs to the FPGA has the following paramenters : L=4, M=4, S=1,
F=2, HD=0, N=16, NP=16. The JESD204 line rate is configured to be 2.5GHz.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
The coraz7s has an Arduino/chipKIT Shield connector with 6 Single-ended
and 8 Differential Analog inputs tied to Xilinx's XADC.
The CN0540 uses the A0-5 pins as single-ended ADC channels to monitor
the differential input, ADC driver, and buffer voltages.
Signed-off-by: Sergiu Cuciurean <sergiu.cuciurean@analog.com>
Note, the current SCLK to spi_clk ratio is four. That means, the input
delay in the MISO line is 25% of the SCLK period.
If the SCLK to spi_clk ratio is changing, this constraint must be
updated.
Generate a higher frequency of spi_clk using an axi_clkgen. (MMCM)
CAUTION: ad7768-1 is still violating the standard SPI timing,
reducing the timing window significantly for the last bit (or last high
bit).
Ignore the following critical warning on DMAC instance:
Critical Warning (15003): "mixed_port_feed_through_mode" parameter of RAM atom
system_bd:i_system_bd|axi_dmac:axi_dmac_0|axi_dmac_transfer:i_transfer| \
dmac_request_arb:i_request_arb|dmac_dest_mm_axi:i_dest_dma_mm| \
altsyncram:bl_mem_rtl_0|altsyncram_0tp1:auto_generated|ram_block1a1
cannot have value "old" when different read and write clocks are used.
Due to the interface differences between HPS's AXI4 and DMA's AXI4, the
tool will try to automaticaly add some bridges between the two
interface. Unfortunatly it does generate timing issues at the f2sdram0
interface of the HPS instance. By explicitly instantiating an AXI
bridge, these timing issues disappears.
The reconfiguration interface for the Stratix10 XCVR has a different
address width. Prepare the register map layout of the project to support
this new architecture.
If we have a lot of peripherals connected to the CPU's memory interface,
the generated interconnect can grow to much decreasing the timing
margin.
One solution is to group the peripherals by its interface types and
functions and use bridges to connect them to the memory interface.
This commit adds the possibility to insert an Avalon Memory Mapped
bridge when we create the connection between the peripheral and CPU.
Should be used just with Avalaon Memory Mapped interfaces.
The ADRV9002 uses in the digital interface 1.8V, however the Zed VADJ is
selectable by a jumper can go up to 3.3V . Voltage levels higher than 1.8V
are detected by the EVAL-ADRV9002 board, asserting the VADJ_ERR pin.
If VADJ error is set high keep all drivers in high-z state and signalize
it to the software layer through a gpio line.
All input and output delays should be referenced to a virtual clock.
If the input and output delays reference base clocks or PLL clocks rather than
virtual clocks, the intra- and inter-clock transfer clock uncertainties,
determined by derive_clock_uncertainty, are incorrectly applied to the I/O ports.
See mnl_timequest_cookbook.pdf for more info.
By defualt the supported tool chain is Quartus PRO. If you want to
build the project with Quartus Standard, you need to define an environment
variable called QUARTUS_PRO_ISUSED with the value 0. (e.g. export
QUARTUS_PRO_ISUSED=0 )
Note: Not all projects going to build on Quartus Standard, you should
fix the errors if there is any.
There is a major compatibility issue between 2019.1 and 2019.2.
The file system_top.hdf got a different file extention. This will
cause a compilation failer in the end of the build. To save time
and fail earlier, upgrade the version mismatch message to ERROR.
If user still wants to build a branch with different tool version
the variable ADI_IGNORE_VERSION_CHECK should be set to 1.
On the Xilinx PHY the available PLL options depends on the lane rate.
Encoding is:
0 - CPLL
1 - QPLL0
2 - QPLL1
Since the selection of line rate is available from the project also the
PLL selection must be exposed.
The AFE's I2C interface should be pin-multiplexed to the FPGA. Also, add
a bidirectional IO buffer for the interface, and make sure it has weak
pull-up resistors.
Use over-writable parameters from the environment.
e.g.
make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4
make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4
make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8
The previous mechanism was "probing" the DMAs for valid data. Better said,
each interpolation channel enabled it's DMA until a valid data was received,
then it disabled the DMA read and waited for the adjacent channel(DMA) to
receive a valid data. Only when for both channels had valid data on the
DMAs interfaces was the transmission started. This added an undesired and
redundant complexity to the interpolation channels. Furthermore, for continuous
transmission, using the above mechanism lead to a fixed phase(sample)
shift between the two channels at each start.
By using the streaming mechanism the interface is simplified and the
above problems are solved.
Because fmcomms2 was not supported on a Intel carriers the
fmcomms2_qsys.tcl file got outdated.
The arradio project has the same hdl design. Hence the update is
merely a copy of the arradio_qsys.tcl with small changes.
This commit fixes the critical warning regarding the missing clock
definitions.
- Defined MDC(MDIO) clocks
- Set false path on(to) the ps8 MDIO input pins. There are synchronization
stages in the GMII to RGMII converter for the CDC between the 375M refclk
and 2.5M MDC clock domains.
implemented mux for temp reading either from internal or external
source; updated regmap; added param to identify source for temp
information; updated tacho measurements; added AVG_POW param used
for tacho measuremet average useful for simulations; defaults for
tacho measurements changed to params and added registers; added
prescaler for fsm control, FSM updated; changed register write
process; connected INTERNAL_SYSMONE to regmap, value can now be
read by software;
Because of the rmii mode requirements(external 50MHz clock) the
board will have the rx_err signal replaced on the FMC connector with the
50MHz external clock (D08/D20).
The rx_er will be shifted to the D9/D21 pins.
The IO location of the laser_driver_otw_n was moved from FMC_HPC_LA27_N
to FMC_HPC_LA31 (laser_gpio[12]).
laser_gpio[11:0] assignments were shifted with one bit to MSB, and laser_gpio[0]
got the old location of the laser_driver_otw_n.
When channels are not swapped in groups of four but are completely out of order
the common control channel can't be reordered based on the index of the
channel.
The DDR controller for C2 for is much closer to the transceivers which
connect to the FMCp connector so designs does not have to span over all
three SLRs just over two reducing implementation and timing closure effort.
The second ADC was removed from the project, as the EV-AD7768-1FMCZ evaluation
board contains only one ADC. Therefore, all the IPs related to the
second ADC have been removed, too.
The data width supported by the spi IPs has been changed from 8 bits to
32 bits, therefore the axis_upscaler(util_axis_upscale_v1_0) and the
m_axis_samples_24(AXI4-Stream Data Width Converter) are no more necessary,
so they have been removed from the design.
The 24 bits width data transfer between the s_axis of axi_ad77681_dma
(AXI DMA Controller) and the offload_sdi of the spi_engine_offload is now made
directly.
Add commands to generate one extra file with resource utilization, in CSV format.
New commands executes only if ADI_GENERATE_UTILIZATION env variable is set.
In ZCU102 LA01_CC_P|N are connected to regional clock, but in order to
receive a device clock properly we have to use pin which is connected
to a global clock buffer. Luckily SYSREF is connected to global clock
pin; swap to port to receive the device clock correctly.
Also, swap the ports in both ZC706 and A10SOC carriers.
mclk now generated by ps not axi clkgen ip. ADAU1761 expects a free
running clock and the i2s driver was switching the axi clkgen ip off
which was causing issues.
Cleanup placement constraints and let the tool have more freedom to
place and route the design. This is possible only after balancing the
memory and system clocks.
Minimize skew on synchronous CDC timing paths between clocks originating
from the same MMCM source. (sys_mem_clk and sys_cpu_clk)
This is required mostly by the smart interconnect.
The CLOCK_DELAY_GROUP property must be applied directly to the output net of BUFGs.
"prepare_incremental_compile" is defined as a phony target, but is also a
prerequisite of a real target. This will lead to a complete project build
every time make is called.
To fix the issue the functionality of prepare_incremental_compile target
was included in the generic project build target.
Software has to know which TIA channel was used for a particular capture.
Define an additional dummy ADC channel which will provide this
information. Currently this channel is always enabled.
This commit was created by squashing the following commits, these
messages were kept just for sake of history:
ad9694_500ebz: Mirror the SPI interface to FMCB
ad9694_500ebz: Set transceiver reference clock to 250
ad9694_500ebz: Allow to configure number of lanes, number of converters
and sample rate
axi_ad9694: Fix number of lanes, it must be 2
ad9694_500ebz: Update the mirrored spi pin assignments
ad9694_500ebz: Gate SPI MISO signals based on chip-select
ad9694_500ebz: Set channel pack sample width
ad9694_500ebz: Change reference clock location
ad9694_500ebz: Remove transceiver memory map arbitration
ad9694_500ebz: Ensure ADC FIFO DMA_DATA_WIDTH is not larger ADC_DATA_WIDTH
ad9694_500ebz: Adjust breakout board pin locations
ad_fmclidar1_ebz: Rename the ad9694_500ebz project
ad_fmclidar1_ebz: Fix lane mapping
ad_fmclidar1_ebz: Delete deprecated files
ad_fmclidar1_ebz: Integrate the axi_laser_driver into the design
ad_fmclidar1_ebz: OTW is an active low signal
ad_fmclidar1_ebz: zc706: Fix iic_dac signals assignment
ad_fmclidar1_ebz: Switch to util_adcfifo
ad_fmclidar1_ebz: Enable synced capture for the fifo
ad_fmclidar1_ebz/zc706: Enable CAPTURE_TILL_FULL
ad_fmclidar1_ebz/zc706: Reduce FIFO size to 2kB
ad_fmclidar1_ebz: Laser driver runs on ADC's core clock
ad_fmclidar1_ebz_bd: Delete the FIFO instance
Because the DMA transfers are going to be relatively small (< 2kbyte),
the DMA can handle the data rate, even when the frequency of the laser
driver pulse is set to its maximum value. (200 kHz)
The synchronization will be done by connecting the generated pulse to
the DMA's SYNC input. Although, to support 2 or 1 channel scenarios, we
need to use the util_axis_syncgen module to make sure that the DMA
catches the pulse, in cases when the pulse width is too narrow. (SYNC is
captures when valid and ready is asserted)
Also we have to reset the cpack IP before each pulse, to keep the DMA buffer's
relative starting point in time fixed, when only 2 or 1 channel is
active.
Our internal repository was changed from phdl to ghdl. Update the
adi_env.tcl scripts and other scripts, which depends on the $ad_ghdl_dir
variable. This way the tools will see all the internal IPs too.
Vivado can not apply the IOB TRUE constraint to only one bit of a
registers. So these constraints will generate several CRITICAL WARNING.
Taking into consideration the maximum used frequencies and current
architecture these constraints are not critical.
Initial version of AD5758 SDZ evaluation board support on ZedBoard.
No critical warnings in the Vivado log.
Bitstream generation passing.
Bring-up on actual board not done.
In the latest system_top file we are not bringing out all the interrupt
signals from the block design. Delete all interrupt ports from the
system_wrapper instance.
Following projects were changed:
- AD5766_SDZ
- AD7134_FMC
- AD7616_SDZ
- AD77681EVB
- AD7768EVB
- ADAQ7980
Observation and RX should never run at the same time.
Given that there is no FIFO on the RX and OBS paths, they will use the higheste performance HP ports, which are HP1 and HP2
For all the Xilinx base design, define three global clock nets, which
are saved in the following three global variable: $sys_cpu_clk, $sys_dma_clk
and $sys_iodelay_clk.
These clock nets are connected to different clock sources depending of
the FPGA architecture used on the carrier. In general the following
frequencies are used:
- sys_cpu_clk - 100MHz
- sys_dma_clk - 200MHz or 250Mhz
- sys_iodelay_clk - 200MHz or 500Mhz
Define a MIMO_ENABLE parameter for the core, which will insert
and additional de-skew logic to prevent timing issues coming from
the clock skew differences of two or multiple AD9361.
Add support for the Arria 10 SoC development kit to the dac_fmc_ebz
project.
This allows to use the following FMC boards on the Arria 10 SoC development
Kit carrier:
* AD9135-FMC-EBZ
* AD9136-FMC-EBZ
* AD9144-FMC-EBZ
* AD9152-FMC-EBZ
* AD9154-FMC-EBZ
* AD9171-FMC-EBZ
* AD9172-FMC-EBZ
* AD9173-FMC-EBZ
Note that the board in its default configuration is not fully compatible with the
mentioned FMC boards and some slight re-work moving some 0 Ohm resistors is
required. The rework concerns the LA01 and LA05 pins, which by default are
not connected to the FPGA. The changes required are:
LA01_P_CC
R612: R0 -> DNI
R610: DNI -> R0
LA01_N_CC
R613: R0 -> DNI
R611: DNI -> R0
LA05_P
R621: R0 -> DNI
R620: DNI -> R0
LA05_N
R633: R0 -> DNI
R632: DNI -> R0
The main differences between AD9144-FMC-EBZ and AD9172-FMC-EBZ are:
* The DAC txen signals are connected to different pins
* The polarity of the spi_en signal is active low instead of active high
* The maximum lane rate is up to 15.4 Gpbs
To accommodate this all 4 possible txen signals as well as the spi_en
signal are connected to GPIOs. Software can decide how to use them
depending on which FMC board is connected.
Note that each carrier has a maximum supported lane rate. Modes of the
AD9172 (and similar) that exceed the carrier specific limit can not be used
on that carrier. The limits are as following:
* A10SoC: 14.2 Gbps
Add a generic project for the AD91xx-FMC-EBZ DAC boards connected to the
ZCU102 and ZC706 carrier boards.
The project is called dac_fmc_ebz as the intention is to support all DAC
FMC evaluation boards with this project since they are sufficiently similar
to be supported by the same design.
This project will successively extended to add support for more boards.
The desired DAC device and JESD operation mode must be selected from the following
file:
./common/config.tcl
This design can support the following FMC boards which are all pin
compatible:
* AD9135-FMC-EBZ
* AD9136-FMC-EBZ
* AD9144-FMC-EBZ
* AD9152-FMC-EBZ
* AD9154-FMC-EBZ
* AD916x-FMC-EBZ
* AD9171-FMC-EBZ
* AD9172-FMC-EBZ
* AD9173-FMC-EBZ
Note that the AD9152-FMC-EBZ only uses the first 4 lanes, whereas all other
boards use 8 lanes.
This project assumes that the transceiver reference clock and SYSREF are
provided via the clock distribution chip that is found on the
ADxxxx-FMC-EBZ board.
In terms of pin connections between the FPGA and the FMC board the
AD9172-FMC-EBZ is very similar to the AD9144-FMC-EBZ.
The main differences are:
* The DAC txen signals are connected to different pins
* The polarity of the spi_en signal is active low instead of active high
* The maximum lane rate is up to 15.4 Gpbs
To accommodate this 5 txctrl signals as well as the spi_en signal are connected
to GPIOs. Software can decide how to use them depending on which FMC board
is connected.
Note that each carrier has a maximum supported lane rate. Modes of the
AD9172 (and similar) that exceed the carrier specific limit can not be used
on that carrier. The limits are as following:
* ZC706: 10.3125 Gbps
* ZCU102: 15.4 Gbps (max AD9172 lanerate)
* SPI and GPIOs to PMOD header support
Connect a SPI interface and some GPIOs to the PL PMOD headers on the zcu102
and zc706 carriers.
This is can be used to control additional external hardware like a clock
chip or an analog front-end.
This is especially useful on FMC boards that do not feature a clock
generator chip.
The pin out is:
PMOD 1: SPI clock
PMOD 2: SPI chipselect
PMOD 3: SPI MOSI
PMOD 4: SPI MISO
PMOD 7: GPIO 0
PMOD 8: GPIO 1
PMOD 9: GPIO 2
PMOD 10: GPIO 3
The GPIOs are mapped at offset 48-51 of the EMIO GPIOs.
Add a clock crossing bridge for the interfaces that runs on a different
clock than the emif_user_clk.
This way we can simplify the main interconnect, and prevent occasional
timing violations.
The process ad_xcvrcon has a device_clk attribute which can be used to
connect a custom device clock to the XCVR. Fix the proc call so we can
simplify the block design script.
The process ad_xcvrcon has a device_clk attribute which can be used to
connect a custom device clock to the XCVR. Fix the proc call so we can
simplify the block design script.
After the previous commit that removed the interconnects from HP ports
in order to reduce utilization. The directly connected DMAs were not
assigned to a specific range and address.
Allow the top level files to have parameters.
Pass the parameters from system_project.tcl to the Vivado/Quartus project and
to the block design scripts through ad_project_params variable.
Usage:
1. create a project with a list of parameters:
adi_project_xilinx my_project [list PARAM_A PARAM_A_VALUE PARAM_B PARAM_B_VALUE]
or
adi_project_altera my_project [list PARAM_A PARAM_A_VALUE PARAM_B PARAM_B_VALUE]
2. access the parameter in QSYS or block design through the $ad_project_params variable
e.g
set PARAM_A $ad_project_params(PARAM_A)
set PARAM_B $ad_project_params(PARAM_B)
3. In system_top.v use PARAM_A and PARAM_B as parameters/generics
Look for undefined clocks which do not show up in the timing summary
therefore can lead to silent failures.
If clocks are not defined they are not analyzed during the timing
checks.
This commit add support for the dual AD9208-DUAL-EBZ board.
The clocking scheme is different from the other projects.
The device clock (LaneRate/40) is no longer an output of the transceivers (RXOUTCLOCK),
it is received directly from the clockchip SCLKOUT9 output through the REFCLK1.
This is needed for deterministic latency where SYSREF must be sampled
with the device clock by meeting setup and hold time.
The two channels from each converter are merged together and transferred to the DDR with a single DMA.
It has all transceiver parameters set for a 15Gpbs lane rate and uses the QPLL.
REQUIRED HARDWARE CHANGES : The F1 2A fuse must be populated on the FMC
board.
Clear the reference checkpoint if the incremental compilation is not
selected through the make option. Other case the scripts will silently
use the reference.dcp checkpoint if that exists.
The scripts are looking for a previous run result, a routed design
checkpoint to use it as a reference during the incremental build flow.
Before clearing the project files, the scrips will save the reference dcp
file in the project folder.
If the reference dcp does not exists the build continues normally.
Proposed workflow:
1. Build your project normally with 'make' or place manually a
reference.dcp file in the Vivado project folder.
2. Do some minor modifications
3. Run the make with the following option:
make MODE=incr
4. Repeat steps 2-3
Using a common IP cache location for all the project will speed up
compile time of common blocks used in base designs. Example a MicroBlaze
core for VCU118 once compiled it will be reused on other projects.
Using a common IP cache will speed up re-compiles of every project in OOC
mode since the cache won't be cleared as with normal compile flow.
Having a clock assigned manually to the clk output pin of the axi_ad9361
let the Vivado timing engine to not ignore the clock insertion delay when
analyzing paths between clk_0 and the manually created clock that has
the same source (clk_0), resulting in timing failure.
In the current form, when connecting a master to the HP ports all
available slave address spaces are mapped to the master (DDR_*, PCIE*, OCM,
QSPI)
Let the PL masters have access only to the DDR_LOW and DDR_HIGH address
spaces to avoid unnecessary resource usage and increase timing margin.
Create the dacfifo/adcfifo infrastructure with procedures.
This will allow moving the parameters of the dac/adcfifo inside
the block design so it can be calculated based on other parameters.
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.
Signed-off-by: Matt Fornero <matt.fornero@mathworks.com>
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.
Signed-off-by: Matt Fornero <matt.fornero@mathworks.com>
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When we improve timing by modifying the implementation strategies,
the general rule of thumb is "less is always more".
Timing did not fail in synthesis, so we leaving the synthesis
strategy in default.
After several parallel runs with various strategies, the
"Performance_Explore" strategy gave the best result for
implementation.
Each individual link of a multi-link has its own sync signal. The top level
sync port that is created by the ad_xcvrcon function is always a single bit
single though.
This results in only the sync signal of the first link being routed while
others are ignored.
To fix this make sure that for multi-link setups the sync port is a vector
port with the width equal to the number of links.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
- refclk and refclk_rst were used for ethernet IDELAY, but are not needed anymore
- muxaddr_out pins overlap with regular GPIOs in the Zed base design. The XADC mux GPIOs can be controlled through that. Cusomters that want to directly control the pins through XADC IP must modify the design
In default strategy we having a few path with small negative slack inside of
the MIG, due to the high UI clock (300MHz).
This new strategy solves this issue.
Add support for specifying a set of parameter value pairs when
instantiating an IP core to the ad_ip_instance command. This has the
convenience of not having to repeatedly call ad_ip_parameter with the name
of the core that got just created for each parameter that needs to be set.
It is also useful for cases where some parameters have mutually exclusive
values and both (or more) have to be set at the same time.
This also slightly speeds things up. Whenever a parameter is changed the
core needs to be updated and post configuration scripts might run. When
setting all parameters at the same time this only happens once instead of
once for each parameter.
For example the following sequence
ad_ip_instance axi_dmac axi_ad9136_dma
ad_ip_parameter axi_ad9136_dma CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter axi_ad9136_dma CONFIG.DMA_TYPE_DEST 1
ad_ip_parameter axi_ad9136_dma CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_parameter axi_ad9136_dma CONFIG.DMA_DATA_WIDTH_DEST 256
can now be replaced with
ad_ip_instance axi_dmac axi_ad9136_dma [list \
DMA_TYPE_SRC 0 \
DMA_TYPE_DEST 1 \
DMA_DATA_WIDTH_SRC 64 \
DMA_DATA_WIDTH_DEST 256 \
]
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The loopback on the unused gpio inputs consumes routing resources
while does not gives any value for the software.
Connect these lines to zero instead.
Some projects use the ad_iobuf on IOs that are not bidirectional
producing synthesis warnings.
The change fixes warnings like:
[Synth 8-6104] Input port 'gpio_bd_i' has an internal driver
[Synth 8-6104] Input port 'gpio_status' has an internal driver
- connect unused GPIO inputs to loopback
- connect unconnected inputs to zero
- complete interface for system_wrapper instantiated in all system_top
fixes incomplet portlist WARNING [Synth 8-350]
fixes undriven inputs WARNING [Synth 8-3295]
The change excludes the generated system.v and Xilinx files.
- remove interrupts from system_top
- for all suported carriers:
- remove all interrupt bd pins
- connect to GND all initial unconnected interrupt pins
- update ad_cpu_interrupt procedure to disconnect a interrupt from GND
before connectiong it to another pin.
Just one VCC or GND xlconstant will be generated for each width. This
way we can avoid having a lot of xlconstant instances with the same
configuration.
Some FMC boards do utilize more than one transceiver quad but do not
necessarily use all transceivers in a quad. On such board is the
AD9694-500EBZ. Which uses two transceivers each in two adjacent quads.
This board can not be supported by instantiating a util_adxcvr with only 4
lanes. Since those 4 lanes would be packed into the same quad. Instead it
it is necessary to instantiate a util_adxcvr with 6 lanes. 4 lanes for the
first quad and 2 for the second.
To still to be able to connect such a util_adxcvr to a link layer with only
4 lanes allow to specify sparse lane mappings. A sparse mapping can have
less lanes than the util_adxcvr and some lanes will be left unconnected.
For example for the AD9694-500EBZ the lane mapping looks like the following:
ad_xcvrcon util_ad9694_xcvr axi_ad9694_xcvr ad9694_jesd {0 1 4 5} rx_device_clk
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Sometimes the output clock of the transceiver should not be used for the
device clock.
E.g. for deterministic latency with no uncertainty the device clock needs
to be sourced directly from a clock or transceiver reference clock input
pin.
Add an option to the ad_xcvrcon command to specify the device clock.
In case the same device clock is used for multiple JESD204 links, e.g. a TX
and a RX link only one reset generator is created.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This change adds the TLAST signal to the AXI streaming interface
of the source side for Intel targets.
Xilinx based designs already have this since the tlast is part of the
interface definition.
In order to make the signal optional and let the tool connect a
default value to the it, the USE_TLAST_SRC/DEST parameter is
added to the configuration UI. This conditions the tlast port on
the interface of the DMAC.
Xilinx handles the optional signals much better so the parameter
is not required there.
There are random timing violations on the A10GX board using the
DAQ3 and DAQ2 projects.
Setting the synthesis/implementation strategy to "HIGH PERFORMANCE
EFFORT" increases the success rate of the timing closure significantly.
In the system top of the FMCOMMS5 projects, there are several GPIO lines, which
can not find in the constraint file, respectively gpio_open_15_15,
gpio_open_44_44 and gpio_45_45.
These are floating GPIO pins, as their names suggest. Delete all these wires and
update IOBUF instances.
Moved XCVR related connections to HP0, where the HP shares the MUX with the Video DMA
HP1 and HP2 are used for RX OS and RX DMAs, sharing the MUX. Usually they shouldn't run at the same time.
HP3 is used for TX DMA, sharing the MUX with the FPD DMA controller
All HPx and DMA buswidths have been increased to 128 bits
The HPx-DMA clock has been increased to 300 MHz
DAC FIFO address size has been increased to 17
In DUAL mode half of the data ports are unused and the unused inputs need
to be connected to dummy signals.
Completely hide the unused ports in DUAL mode to remove that requirement.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Connect the DAC data underflow pin (fifo_rd_underflow) of the DMA
to the dunf pin of the device core. This way the software can detect
underflows in the DAC data path.
Connect the DAC data underflow pin (fifo_rd_underflow) of the DMA
to the dunf pin of the device core. This way the software can detect
underflows in the DAC data path.
Connect the DAC data underflow pin (fifo_rd_underflow) of the DMA
to the dunf pin of the device core. This way the software can detect
underflows in the DAC data path.
sergiu arpadi
Istvan Csomortani
Adrian Costina
Laszlo Nagy
hotoleanudan
Sergiu Cuciurean
Stanca Pop
stefan.raus
AndreiGrozav
Stanca.Pop
Dragos Bogdan
StancaPop
István Csomortáni
Prasahnt Sivarajah
Lars-Peter Clausen
Matt Fornero