c11d7d9fda
rfsom2/ccbox- tsw s5 fix
2017-07-19 14:23:54 -04:00
d969b9ea9f
rfsom2/ccbox- tsw updates
2017-07-18 13:53:44 -04:00
becc3e8628
rfsom/ccbox- tsw updates
2017-07-18 13:51:37 -04:00
2e173201d4
daq2: daq2_qsys.tcl: Use sys_dma_clk
...
Use the sys_dma_clk clock module for clock and reset signals of the data
path, rather than using the A10GX specific sys_ddr3_cntrl signals. This
enables compatibility for all Altera/Intel platforms.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-17 17:38:20 +02:00
711cb66985
adrv9371x: Write parameter as hexa value to clear Vivados ambiguity between decimal and binary
2017-07-14 10:20:57 +03:00
98cf18dd51
daq3/zc706: Fix system_top instantiation
...
Delete used interrupt ports: the ps_intr_10 and ps_intr_11 is used by
the jesd cores.
2017-07-06 13:29:09 +01:00
b4a25223fa
plddr3_dacfifo_bd: Increase the AXI burst length to max
...
Increase AXI burst length to maximum value, to support higher
data rates.
2017-07-06 10:15:06 +01:00
debca3a153
fmcjesdadc1: vc707: Remove unsed mb_intrs signal
...
The mb_intrs signal is never driven, it is a leftover of an earlier version
of the file, remove it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-05 14:38:25 +02:00
0360e8587e
Connect JESD204 interrupts
...
Connect the ADI JESD204 link layer peripheral interrupt signals in all
projects.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-05 14:37:50 +02:00
b0ebf2df06
daq3: Provide DAC JESD204 lane mapping
...
The DAQ3 does not use a 1-to-1 lane mapping for the DAC JESD204 link.
Provide the proper mapping when setting up the transceiver connections.
Without this the payload data will be mapped incorrectly and the
transmitted signals are scrambled.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-30 16:01:10 +02:00
d65a543854
kc705: Fix ethernet address span
2017-06-30 14:23:01 +03:00
a765a9c709
arradio: Add i2c interface
2017-06-29 17:26:58 +03:00
6ebef5dde0
make: Update make files
2017-06-26 15:51:19 +01:00
ca12938873
ad77681evb: Suppress a critical warning
2017-06-22 14:25:43 +01:00
1541943ff2
adrv9371_alt: Delete the fifos from the RX path
...
+ Delete the rx_fifo and rx_os_fifo from the RX datapath
+ Change the receive DMA's source interface type to wr_fifo
2017-06-22 11:58:10 +01:00
2e8be3d7a6
daq2: Provide DAC lane map
...
Provide the correct lane mapping for the DAQ2 DAC lanes which do not follow
a 1-to-1 mapping between physical and logical lanes due to PCB layout
constraints.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
4bf5990451
adi_board.tcl: ad_xcvrcon: Add lane mapping support
...
Add a parameter to the ad_xcvrcon function that allows to provide a mapping
between logical and physical lanes. By default if no lane map is provided
the logial and physical lanes are mapped 1-to-1. If a lane map is provided
logical lane $n is mapped onto physical lane $lane_map[$n].
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
56867b362e
daq3- updated to 12.5G
2017-06-16 09:02:26 -04:00
3fb5408acc
fmcjesdadc1/a10gx- fix sysref, lvds io and such
2017-06-15 13:57:21 -04:00
6ec9eab7b9
fmcjesdadc1/a10soc- fix sysref, lvds io and such
2017-06-15 13:57:21 -04:00
ef290ef484
hdlmake.pl updates
2017-06-15 11:42:44 -04:00
e33e6a84f4
a5gt/a5soc - removed
2017-06-15 11:41:28 -04:00
a23fb793a0
a5gt/a5soc - removed
2017-06-15 11:40:58 -04:00
2649458b6d
hdlmake.pl updates
2017-06-15 10:21:57 -04:00
fd0c7f1b1c
usdrx1/a10gx- updated to a10gx
2017-06-15 10:21:57 -04:00
0311ed411c
usdrx1/a10gx- added
2017-06-15 10:21:57 -04:00
7ac083b932
fmcjesdadc1/a10soc- sysref fixes
2017-06-15 10:15:59 -04:00
004aee930b
fmcjesdadc1/a10gx- fix sysref, gpio connections
2017-06-14 14:40:23 -04:00
dba419239b
hdlmake.pl updates
2017-06-14 10:41:14 -04:00
3299d244fe
fmcjesdadc1: a10gx/a10soc
2017-06-14 10:39:57 -04:00
38c708d4d0
fmcjesdadc1: a10gx/a10soc
2017-06-14 10:39:38 -04:00
051c1d6644
fmcjesdadc1: a10soc
2017-06-13 15:00:22 -04:00
c1bc1259a7
fmcjesdadc1: a10gx
2017-06-13 12:39:45 -04:00
3f3ea5f99a
hdlmake.pl- updates
2017-06-13 09:55:08 -04:00
ffb6cd4b0b
scripts- add a5soc device
2017-06-13 09:54:01 -04:00
ff646b0cfc
common/a5soc- alt 16.1 updates
2017-06-13 09:54:01 -04:00
0eacde9158
fmcjesdadc1/a5soc- alt 16.1 updates
2017-06-13 09:54:01 -04:00
6decba3c3b
hdlmake.pl updates
2017-06-09 16:23:17 -04:00
74f9a99655
fmcjesdadc1/a5gt- altera 16.1 updates
2017-06-09 16:20:49 -04:00
2e17e67627
common/a5gt- altera 16.1 updates
2017-06-09 16:20:15 -04:00
688758e6c6
scripts/adi_project_alt- add a5soc, a5gt
2017-06-09 16:19:29 -04:00
ca536d50ac
altera 16.1 c5soc updates
2017-06-08 15:03:03 -04:00
f3af192f30
altera 16.1 arradio updates
2017-06-08 15:02:46 -04:00
ca20309166
adi_project_alt: add c5soc
2017-06-08 15:02:24 -04:00
b8a75a7285
hdlmake.pl - updates
2017-06-07 10:23:20 -04:00
6100a697e8
daq3/a10gx- alt 16.1 updates
2017-06-07 10:23:20 -04:00
40bfd0380e
adrv9371x/a10gx- alt 16.1 updates
2017-06-07 09:19:14 -04:00
83747ddb33
ad77681evb: Fix IO constraints
2017-06-07 14:28:39 +03:00
b7ca17f02b
scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects
2017-06-07 12:06:50 +03:00
d1bab7ddb9
hdlmake.pl- updates
2017-06-06 16:10:05 -04:00
Rejeesh Kutty
Lars-Peter Clausen
Adrian Costina
Istvan Csomortani
AndreiGrozav