Commit Graph

182 Commits (c15c82d9d180f6c2bffeadbb4210fd98282a6acb)

Author SHA1 Message Date
Istvan Csomortani 2345d29663 fmcomms2: Update make files 2015-11-11 11:15:45 +02:00
Istvan Csomortani a936ad607f fmcomms2/zc706: Delete unused files from file list 2015-11-11 11:14:58 +02:00
Istvan Csomortani c7e86528d6 fmcomms2/zc706: Cosmetic changes on constraints file 2015-11-11 11:14:16 +02:00
Istvan Csomortani 6197a82c80 fmcomms2/common: Add the util_tdd_sync module 2015-11-11 11:07:15 +02:00
Adrian Costina 9d2b8809df Makefiles: Updated Makefiles 2015-10-23 10:44:27 +03:00
Istvan Csomortani 21737ad7b8 fmcomms2/zc706pr: Update the fifo interface of the PR module 2015-10-13 11:37:44 +03:00
Istvan Csomortani c9a5057b93 library/prcfg : Split data bus to channels
Because of the new pack/upack modules on the data path, it makes more sense to split the data interface of the PR modules into separate channels.
The top module will supports max 4 channels.
2015-10-13 11:36:45 +03:00
Istvan Csomortani c83239b014 fmcomms2/zc706pr: Update PR design
+ Add system_top.v to design
+ Add pr specific constraints
2015-10-09 13:23:42 +03:00
Istvan Csomortani f77f928444 fmcomms2/zed: Fix the system_top
Fix the enable/txnrx control line.
2015-09-25 19:11:41 +03:00
Istvan Csomortani aeb1d7aa3e fmcomms2/zed: Cosmetic changes 2015-09-25 19:11:39 +03:00
Istvan Csomortani f8b3096bd0 fmcomms2/vc707: Fix the system_top
Fix the enable/txnrx control lines.
2015-09-25 19:11:37 +03:00
Istvan Csomortani 2c75cfd04e fmcomms2/vc707: Cosmetic changes 2015-09-25 19:11:35 +03:00
Istvan Csomortani ffa0bcd19f fmcomms2/mitx045: Fix the system_top
Fix the enable/txnrx control lines.
2015-09-25 19:11:32 +03:00
Istvan Csomortani 28d20e84c5 fmcomms2/zc702: Fix the system_top
Fix the enable/txnrx control lines.
2015-09-25 19:11:30 +03:00
Istvan Csomortani ea74413125 fmcomms2/kc705: Fix the system_top.
Fix the enable/txnrx control lines.
2015-09-25 19:11:28 +03:00
Istvan Csomortani f80622b972 fmcomms2/ac701: Fix the system_top
Fix the enable/txnrx control line.
2015-09-25 19:11:26 +03:00
Lars-Peter Clausen cd8b467b1e fmcomms2: Drop explicit axi_dmac clock synchronicity configuration
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:07 +02:00
Istvan Csomortani a679251d7d Makefiles: Update Make 2015-09-09 17:13:19 +03:00
Istvan Csomortani 510f1cfdd9 fmcomms2_zc706: Update project with the new TDD sync interface 2015-09-09 12:35:22 +03:00
Rejeesh Kutty a92e049e8f fmcomms2_bd- another attempt at ila width 2015-08-27 13:17:08 -04:00
Rejeesh Kutty b8f9b7040d fmcomms2- tdd ila fixes 2015-08-27 11:55:41 -04:00
Rejeesh Kutty 026fad8853 fmcomm2- enable/txnrx- through devif 2015-08-27 11:41:58 -04:00
Rejeesh Kutty 6a9790484f fmcomm2- enable/txnrx- through devif 2015-08-27 11:41:56 -04:00
Rejeesh Kutty 2e1e0939ce fmcomms2- dma parameters & ila cores upgrade 2015-08-26 14:12:57 -04:00
Rejeesh Kutty 9e5e7d6805 remove rfsom from fmcomms2 2015-08-20 10:33:43 -04:00
Istvan Csomortani d52308f074 axi_dmac: Change parameter name 2D_TRANSFER
Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 10:14:22 +03:00
Istvan Csomortani 57cfb7cfb1 hdl/library: Update the IP parameters
The following IP parameters were renamed:

PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
Istvan Csomortani 10d9de39a1 axi_ad9361/tdd: Update the synchronization logic
The master will regenerate a sync pulse periodically. The period can be defined by software.
2015-08-19 12:21:23 +03:00
Istvan Csomortani bcee3e04d4 fmcomms2_tdd: Update tdd_enabaled path
This line controls the mux, which switch between hdl and software (GPIO) control of the ENABLE/TXNRX pins.
Fix the broken path and change the name from "tdd_enable" to "tdd_enabled".
2015-08-19 12:14:05 +03:00
Istvan Csomortani d2c99acae8 fmcomms2/TDD: Update synchronization interface
Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 15:14:36 +03:00
Istvan Csomortani 8e631e56d6 fmcomms2: Add a synchronization interface for TDD mode.
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write  0x01 into TDD register 0x50.
2015-07-28 14:42:54 +03:00
Istvan Csomortani 28aea82952 fmcomms2_zc702: Add SPI and GPIO interface for FREQCVT 2015-07-22 10:16:04 +03:00
Adrian Costina a7da779b94 Makefile: Updated Makefiles 2015-07-16 18:19:42 +03:00
Istvan Csomortani 1dcbf5e5a2 fmcomms2/zc706: Fix GPIO connections
Fix GPIO connections for the FREQCVT board.
2015-07-15 15:12:01 +03:00
Istvan Csomortani a38339a3ec fmcomms2/rfsom: Add GPIO control for the RF card 2015-07-14 13:12:54 +03:00
Istvan Csomortani ba2029a6e8 fmcomms2/rfsom: Delete trailing whitespaces from system_constr.xdc 2015-07-14 13:12:53 +03:00
Istvan Csomortani 46fa91d5be Makefile: Update Make files 2015-07-03 18:08:57 +03:00
Istvan Csomortani 95500d4022 fmcomms2_rfsom: Fix GPIO connections 2015-07-03 13:03:19 +03:00
Istvan Csomortani 0102e3e02c fmcomms2_ALL: Preserve backward compatibility for ENABLE/TXNRX control
By default the ENABLE/TXNRX pins are controlled by GPIOs, if the TDD module is enabled, the TDD FSM will take over the control of these two pins.
2015-07-01 13:54:01 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Adrian Costina 25e56a4d03 arradio: renamed fmcomms2 c5soc to arradio 2015-06-08 11:35:21 +03:00
Rejeesh Kutty dc7064ab95 fmcomms2/vc707 - wfifo changes 2015-06-05 12:44:04 -04:00
Istvan Csomortani 25f1ad73f0 fmcomms2/freqcvt: Update SPI interface I/O 2015-06-05 18:16:14 +03:00
Rejeesh Kutty f1e75963a2 fmcomms2: wfifo+pack changes 2015-06-05 09:20:50 -04:00
Istvan Csomortani 3b1ea7e528 axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch
598ece4c8d
2015-06-04 18:09:47 +03:00
Rejeesh Kutty f81d22a17a altera- common timing check 2015-06-04 10:56:32 -04:00
Rejeesh Kutty a6cae6b477 iobuf: do is a system verilog keyword 2015-05-21 14:06:17 -04:00
Lars-Peter Clausen 6b9906b22b Refresh Makefiles
Re-generate the Makefiles after a small update to the generation script:
- Entries are sorted alphabetically
- Empty dependency lines are skipped

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 14:21:54 +02:00
Rejeesh Kutty 0805da3b6b fmcomms2/rfsom- enable dac delay 2015-05-18 16:45:54 -04:00
Rejeesh Kutty 3e51d29f75 enable/txnrx- tdd changes 2015-05-18 14:28:20 -04:00