68461110aa
Replace link in license header from master to main
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2024-01-16 16:48:45 +02:00
7ccc505950
projects/ad7134_fmc: Add FMC pinout description
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* Added txt description of all FMC pins used/unused
* Updated constraint files with FMC pinout location
Signed-off-by: laurentiu_popa <Laurentiu.Popa@analog.com>
2023-10-19 13:56:12 +03:00
c9a7d4d927
Add copyright and license to .tcl, .ttcl files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 15:22:26 +03:00
1cac2d82e1
Add copyright and license to .xdc files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 11:03:02 +03:00
28c06d505f
Add/edit copyright and license for .v, .sv files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-11 15:17:41 +03:00
2ae09c9808
Check guidelines. Remove redundancies
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* Removed empty/commented lines
* Regenerated Makefiles
* Removed redundancies adc channels data width
* Set data width 32-bit: max resolution and CRC header
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-29 15:08:07 +03:00
1bef2bf304
projects/ad7134_fmc: Update bd SPIE hierarchy, spi trigger, ODR
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* Updated bd spi hierarchy, see library/spi_engine.tcl
* Enabled ext_clk for PWM to use 96 MHz spi clk
* Modified PWM channels used:
- ch1: ODR - 850 ns period, 130 ns high time
==> max fODR = 1.18 MHz
- ch0: trigger - 850 ns period, 30 phase shift
==> 10 ns between falling ODR rising DCLK
* Changed spi offload trigger signal:
- replaced edge detect,sync_bits IPs with PWM trigger
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-29 15:08:07 +03:00
db94628cc6
library & projects: Update Makefiles
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-01-27 11:54:05 +02:00
72313df81f
Updated the makefiles to build the projects in subdirectories based on the build parameters.
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Running 'make' will build the default project directly in the project folder (like it did before)
Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory.
Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory.
Running 'make clean' will clean the default project only.
Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build.
Running 'make clean-all' will delete all the built configurations and libraries.
Note that the 'JESD' and 'LANE' words from the parameter names are stripped.
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2022-11-14 09:38:42 +02:00
482f0489a3
scripts: Merge adi_env.tcl into a single file
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Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
961ebe0cc2
projects: Update .v files according to guideline
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Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
4827e5eb18
ad7134_fmc: Switch offload trigger to falling ODR
2022-02-07 14:41:25 +02:00
297bed6721
ad7134_fmc: Change ODR signal to output
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FPGA is now generating the ODR signal using axi_pwm_gen.
Both ADCs are now in slave mode.
2022-02-07 14:41:25 +02:00
591a23156b
Makefiles: Update header with the appropriate license
2021-09-16 16:50:53 +03:00
6f2f2b8626
makefile: Regenerate make files
2021-01-20 01:02:56 +02:00
acbbd4636a
sysid: Upgrade framework, header/ip are now at 2/1.1.a
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Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
9093a8c428
library: Move ad_iobuf to the common library, as it's not Xilinx specific
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Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
d8ab27b2af
sysid: Remove cstring init string
2020-09-30 19:12:24 +03:00
4d54c7e2d6
spi_engine_execution: Merge the SDI lines into one vector
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This modification will help to support multiple SPI engine
execution setups (e.g. different NUM_OF_SDI) for the same project.
2020-05-19 09:28:02 +03:00
32eeedb660
makefile: Update makefiles
2020-05-07 08:41:49 +01:00
c44b4957b5
ad7134_fmc/zed: Fix IO definitions for SDI lines
2019-11-27 10:04:37 +02:00
aa5fdf903e
Makefile: Update makefiles
2019-08-26 16:58:01 +03:00
0680e44330
system_id: deployed ip
2019-08-06 16:53:11 +03:00
a589753d92
project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl
2019-06-29 06:53:51 +03:00
43725429ac
adi_project: Rename the process adi_project_xilinx to adi_project
2019-06-29 06:53:51 +03:00
7fa620d253
gtm_projects: Update system_top
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In the latest system_top file we are not bringing out all the interrupt
signals from the block design. Delete all interrupt ports from the
system_wrapper instance.
Following projects were changed:
- AD5766_SDZ
- AD7134_FMC
- AD7616_SDZ
- AD77681EVB
- AD7768EVB
- ADAQ7980
2019-06-28 11:18:29 +03:00
21ce53f765
Revert "Move GTM projects to gtm_projects branch"
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This reverts commit 171093eca4
2019-06-28 11:18:29 +03:00
171093eca4
Move GTM projects to gtm_projects branch
2018-06-15 16:28:40 +03:00
377247a434
Regenerate project Makefiles using the new shared Makefile includes
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This reduces the amount of boilerplate code that is present in these
Makefiles by a lot.
It also makes it possible to update the Makefile rules in future without
having to re-generate all the Makefiles.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
425e803364
license: Fix a spelling mistake
2018-04-11 15:09:54 +03:00
53fa482837
ad7134_fmc: Initial commit
2018-04-11 15:09:54 +03:00
Iulia Moldovan
laurentiu_popa
Bogdan Luncan
Iacob_Liviu
sergiu arpadi
Adrian Costina
Istvan Csomortani
Lars-Peter Clausen