The project controls the AD3552R digital-to-analog converter and transmits data written in the DDR memory to the QSPI interface of the DAC.
The reference clock is generated by an axi_clkgen IP and is configured to output a 133MHz signal.
If both channels are enabled and data streaming is DDR the sample rate is 16.65MSPS.
If just one channel is enabled and data streaming is DDR the sample rate is 33.3MSPS.
The VADJ voltage should be set to 1.8V.
Signed-off-by: PopPaul2021 <Paul.Pop@analog.com>
The custom interface IP for AD3552R DAC has more operation capabilities:
- 8b register read/write SDR/DDR
- 16b register read/write SDR/DDR
- data stream SDR/DDR ( clk_in/8 or clk_in/4 update rate)
- selectable input source : DMA/ADC/TEST_RAMP
- data out clock(SCLK) has clk_in/8 frequency when the converter is configured and clk_in/2 when the converter is in stream mode
- the IP reference clock (clk_in) can have a maximum frequency of 132MHz
- the IP has multiple device synchronization capability when the DMA is set as an input data source
Signed-off-by: PopPaul2021 <Paul.Pop@analog.com>
-Updated description of some fields of these registers: REG_CHAN_CNTRL_1,
REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4,
and REG_USR_CNTRL_5
-Added two new registers, both with their own fields and description:
REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10
Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
The DDS for each channel was synchronized by the main channel.
One problem with this aporoach is that when a user sets a DDS that
is not from the main channel the sinchronization does not happend.
This behavior is not user friendly in IIO-Oscilloscope or within other
configuration methods.
This commit keeps all channels in sync by triggering the sync on all
channels from each individual channel.
Signals/buses declared in the docs that does not exist in the
components.xml files will raise a warning.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Add documentation info to the README.md
At adi_hdl_parser.py, filter "_signal_clock" and "_signal_reset"
pseudo buses from component.xml files, append them as description
in the ports table, in the format
"{Bus} [...] is synchronous to this {domain}".
Also, adds collapsible directive
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Moves guidelines to user_guide as docs_guidelines.
Includes Porting HDL project user guide.
Replaces the Excel spreadsheet with raw space divided files.
Includes the 6 pinned at the org.
Contributors shall expand the list as needed.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Update link roles to use the "text <link>" standard sphinx syntax.
Add __pycache__ and _build to .gitignore
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Automate table generation for register maps.
Based on tfcollins' vger python scripts.
There are docs/adi_regmap_*.txt with more than one regmap per file,
so the logic changed to allow that.
Using title tool as the unique identifier now.
It has a global option to set the default state (hidden or visible)
for the collpasible tables.
Also remove CSVs.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Uses Vivado generated components.xml files.
If the file is not found/generated, there is a fallback method.
Also, define bibliography per project, not globally.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
The parameters directive allows to almost automatically generate the
parameters table.
It allows to add rich descriptions to the parameters, such as references,
while checking if they exist in the *_hw.tcl file a obtaining the types
and default values.
However, it cannot obtain parameters generated from a foreach loop yet,
making it incompatible with the axi_dmac_hw.tcl file for example.
This commit also joins the other extensions into a single adi_links
extension.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Add support for DDS phase width greather than 16.
The software should read the DDS phase data width register and configure
the DDS init and increment registers accordingly, otherwise the obtained
DDS output frequency will not be the desired one for DDS phase width
different than 16.
DDS_incr = (f_out * 2^(phase_width) * clkratio)/f_if
Change necessary to build intel projects with different system_top verilog files.
This was patterned to ae09b8a1bb/projects/scripts/project-xilinx.mk (L70)
Signed-off-by: Jem Geronimo <Johnerasmusmari.Geronimo@analog.com>
* Removed the commercial JESD license and put the ADIBSD or GPL v2 like
for other Verilog files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
The generic project dependency list contains:
system_top*.v
system_bd.tcl
system_project.tcl
system_constr.xdc
This items will not be included in the auto generated makefiles. But
used as generic dependency.
This commit adds:
-wildcard check of system_constr*.xdc.
-wildcard check of system_constr*.tcl.
Add files CODEOWNERS, filled with owners per each hdl project and some IPs.
Specific code owners will be automatically added as reviewers, whenever new
PRs are opened, depending on affected folders/files from repo.
CODEOWNERS file can be different on each branch.
PULL_REQUEST_TEMPLATE.md content will populate all new PR description field.
Beside PR description, it contains a list of checkboxes, ensuring all
team members follow the same guidelines and enforce best practices.
PR Template applies for PRs against repository's default branch.
Both files were added in .github
Signed-off-by: Stefan Raus <Stefan.Raus@analog.com>
PopPaul2021
Jem Geronimo
Iulia Moldovan
Cristian Mihai Popa
AndreiGrozav
Jorge Marques
Jem Geronimo
alin724
ladace
AndrDragomir
Filip Gherman
Stefan Raus
laurentiu_popa