c9a7d4d927
Add copyright and license to .tcl, .ttcl files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 15:22:26 +03:00
482f0489a3
scripts: Merge adi_env.tcl into a single file
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Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
363494ab9c
library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl
2019-06-29 06:53:51 +03:00
5b5218250b
axi_dacfifo: Move util_dacfifo_bypass module to util_dacfifo IP
2018-10-11 16:57:30 +03:00
74b922f9f8
axi_*: Infer clock and reset signals of an IP
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A clock sink must be connected to clock source, and a reset sink to
reset source, otherwise the tool will throw a synthesis warning.
By properly inferring all the reset and clock signals of an IP, we can
get rid of unwanted warning messages.
The following IPs tcl script was updated:
- axi_ad9434
- axi_hdmi_tx
- util_cpack
- util_adxcvr
- axi_ad6676
- axi_ad9625
- axi_ad9379
- axi_ad9265
- util_tdd_sync
- util_rfifo
- util_wfifo
- axi_ad9361
- axi_ad9467
- util_upack
- axi_dacfifo
- axi_ad9152
- axi_ad9680
- util_clkdiv
- axi_ad9122
- axi_ad9684
- axi_mc_speed
- axi_mc_current_monitor
- axi_mc_controller
- util_gmii_to_rgmii
- util_adxcvr
- axi_ad9379
- axi_hdmi
- library
- axi_fmcadc5_sync
- util_adcfifo
- util_mfifo
- axi_jesd204_rx
- axi_jesd204_tx
- axi_ad9361
- axi_adxcvr_ip
2018-04-11 15:09:54 +03:00
700ed156ab
[axi|avl]_dacfifo: Create a separate bypass module for altera/xilinx
2017-09-25 08:56:40 +01:00
85a7cebc0e
axi_dacfifo: Major update and redesign
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Redesign the axi_dacfifo, to increase the supported datarates.
Major modifications:
+ The FIFO consist of two module: WRITE and READ. The axi_dacfifo_dac
was deprecated.
+ Both the AXI write and AXI read transaction are controlled by two
FSM, to increase redability of the code.
+ Support all the possible burst lengths [0..225], handles the last
fractional burst on both sides correctly.
+ Common reset architecture throughout the design, all the internal
registers and memories are reset on the posedge of dma_xfer_req
+ Delete all Altera related sources, for Altera projects
avl_dacfifo should be used.
WIP: foobar
[WIP]axi_dacfifo: Update
axi_dacfifo: Few minor updates, almost working state
2017-08-22 09:16:21 +01:00
a0b33898d2
axi_dacfifo: Add gray coder/decoder module
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Use gray coder/decoder modules, instead of functions.
This way it can be used paramterized data width on the
coders/decoders.
2017-07-06 10:01:27 +01:00
5fe7a1b100
axi_dacfifo: Move the axi_dac_fifo_bypass module to util_dac_fifo_bypass
2017-04-21 13:23:03 +03:00
c1bdfca4c3
library: Delete all adi_ip_constraint process call
2017-04-06 12:36:47 +03:00
104e9dfcdc
adc/dac-fifo altera cores
2017-02-28 13:30:50 -05:00
1fce57f6c3
axi_dacfifo: Redesign the bypass functionality
2017-02-23 17:32:31 +02:00
9defccef70
dacfifo- axi address map fixes
2016-09-27 14:48:23 -04:00
3b0c1e02fc
axi_dacfifo: Move IP to library/xilinx
2016-09-15 11:38:16 +03:00
Iulia Moldovan
Iacob_Liviu
Istvan Csomortani
Adrian Costina
Rejeesh Kutty