f6594e276e
Bring back AXIS FIFO as a separate module
...
Bring back the AXIS FIFO as a separate module instead of embedding it into
the DMAC module. This makes it possible to use it in other modules outside
of the DMAC.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:06 +02:00
8fc4b0630e
util_axis_resize: Fix typo
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:04 +02:00
cb98e3e151
adcfifo: unused process
2015-04-13 13:31:50 -04:00
95e41e50a6
axi_dmac: Make all clocks asynchronous
2015-04-11 12:04:55 +03:00
7d22399860
util_axis_resize: Fixed makefile
2015-04-09 18:06:56 +03:00
e9bd4b3512
axi_dmac: Updated altera core dependency, changed fifo files location
2015-04-09 17:58:21 +03:00
780455d68c
Makefile: Updated makefiles. Added makefiles for altera
2015-04-09 17:57:06 +03:00
b7d8e38c94
util_dacfifo: General update
...
+ Clean out the code, delete unnecessary flops
+ Add support for channel count (C_CH_CNT)
+ FIFO write (data from DMAC/upack) : valid just when xfer_req is asserted, address is free running, new xfer_req resets the address
+ FIFO read (data to DAC) : free running, reads to max address
2015-04-09 11:43:37 +03:00
668b8bda62
util_axis_resize: Add support for specifying the endianness
...
Add support for specifying whether the lsb of the larger bus are mapped to
the first or the last beat on the smaller bus.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 15:55:17 +02:00
f1eb1c6064
util_axis_resize: Add support for non power-of-two ratios
...
Update the axi_repack core so it can handle non power-of-two ratios between
the input and output stream width. The ratio still needs to be a integer
though.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 15:55:17 +02:00
b6458f9aab
axi_dmac: Move axi_repack block to its own module
...
Move the axi_repack block to its own module. This allows it to use it
outside of the DMA controller.
Also rename it to util_axis_resize to better reflect its function.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 15:55:17 +02:00
8a47d0f94b
adi_ip: Add helper function to add dependency to a IP core
...
Add a helper function that allows to add dependencies to IP cores to the
current IP core, this makes it possible to use a module from the other IP
without having to add the file itself to the current core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 15:52:41 +02:00
88abf98bd6
adi_env.tcl: Make default ad_hdl_dir path detection more robust
...
Instead of using a path relative to the current working directory use a path
relative to the location of the adi_env.tcl script.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 14:43:56 +02:00
bdaad46704
axi_dmac: Remove up_write signal
...
up_write is just an alias for up_wreq these days. Just always use the later
and remove the former.
2015-04-08 14:43:56 +02:00
98609527e3
axi_i2s: Add I2S interface definition
...
Using interface definitions makes it possible to group pins of a peripheral
into a interface pins. This allows us to use connect_bd_intf_net to connect
all pins of the interface instead of having to manually call connect_bd_net
for each for the pins.
Using interface pins also unclutters the connections in the Vivado block
design view a bit.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
86e6f67d4b
util_i2c_mixer: Add I2C interface
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
fa696adc98
util_dac_unpack: Add fifo_wr interface
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
978f41cbe8
util_adc_pack: Add fifo_wr interface
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
6ba0667939
axi_dmac: Add fifo_wr/fifo_rd interfaces
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
c82b186610
Add interface definitions for the fifo_rd and fifo_wr interfaces
...
Using interface definitions makes it possible to group pins of a peripheral
into a interface pins. This allows us to use connect_bd_intf_net to connect
all pins of the interface instead of having to manually call connect_bd_net
for each for the pins.
Using interface pins also unclutters the connections in the Vivado block
design view a bit.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
11cc18be79
adi_ip.tcl: Initialize ip_repo_paths
...
Initialize ip_repo_paths so that when building a peripheral we have access to the interface definitions stored in the repository.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
d17cd22ef1
adi_ip.tcl: Allow to directly specify the vlnv string for adi_add_bus()
...
Modify the adi_add_bus() function to take the full vlnv strings instead of just the bus type.
This makes the function more flexible and e.g. allows to handle buses from other vendors.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
0d0c15df98
axi_adcfifo: fix file names
2015-04-07 16:40:52 -04:00
5f8e9a74ea
makefile: updated
2015-04-07 16:32:01 -04:00
922ea7fb34
util_sync_reset: removed
2015-04-07 16:28:05 -04:00
6d0a2bf64c
axi_adcfifo: added
2015-04-07 16:21:39 -04:00
e73e563a02
util_adcfifo_axi: removed
2015-04-07 16:16:51 -04:00
712becd57f
adcfifo: axi version
2015-04-07 16:16:17 -04:00
4f7f109056
util_adcfifo: added
2015-04-07 16:08:38 -04:00
dfaa6f6571
fifo2s: removed
2015-04-07 16:01:36 -04:00
3c316efbc5
fifo2dac: removed
2015-04-07 16:01:21 -04:00
69cadd46ed
adcfifo_axi: added
2015-04-07 16:00:47 -04:00
056d6bbf40
dacfifo: added
2015-04-07 15:55:29 -04:00
99c124e708
fifo2f: removed
2015-04-07 15:53:22 -04:00
9098e3ebca
fifo: removed
2015-04-07 15:52:31 -04:00
86a70b3054
adcfifo: added
2015-04-07 15:43:02 -04:00
7224ca1f0c
dma: moved
2015-04-07 15:35:47 -04:00
9fa3131858
axi_fifo2dac: Initial commit
...
BRAM fifo for high speed DACs
2015-04-07 17:46:36 +03:00
de2c3764d6
util_upack: Updated IP, added upack_valid and dma_xfer_in/dac_xfer_out ports.
2015-04-07 16:55:25 +03:00
8af60576cd
dma: constraints
2015-04-06 13:38:31 -04:00
f79a152958
Makefiles: updated all makefiles adding clean functionality
2015-04-03 11:57:54 +03:00
ba2e635918
makefile: added
2015-04-01 16:28:20 -04:00
2f41aebaa9
makefile: added
2015-04-01 16:28:19 -04:00
a5f937a96d
makefile: added
2015-04-01 16:28:18 -04:00
8b09fedae9
makefile: added
2015-04-01 16:28:16 -04:00
64601272da
makefile: added
2015-04-01 16:28:15 -04:00
e0c7ad802a
makefile: added
2015-04-01 16:28:14 -04:00
b0db485e0d
makefile: added
2015-04-01 16:28:13 -04:00
a10c7a4245
makefile: added
2015-04-01 16:28:11 -04:00
afb7115b2f
makefile: added
2015-04-01 16:28:10 -04:00
90298816e4
makefile: added
2015-04-01 16:28:09 -04:00
96c81013ac
makefile: added
2015-04-01 16:28:08 -04:00
20280fecbe
makefile: added
2015-04-01 16:28:06 -04:00
8ec8c966b1
makefile: added
2015-04-01 16:28:05 -04:00
63efcbf4ca
makefile: added
2015-04-01 16:28:04 -04:00
1d3129a600
makefile: added
2015-04-01 16:28:03 -04:00
00411a53da
makefile: added
2015-04-01 16:28:01 -04:00
15c25ac45b
makefile: added
2015-04-01 16:28:00 -04:00
a63d4ae65c
makefile: added
2015-04-01 16:27:59 -04:00
4222b35292
makefile: added
2015-04-01 16:27:58 -04:00
9ced8643c6
makefile: added
2015-04-01 16:27:56 -04:00
109a38e0e8
makefile: added
2015-04-01 16:27:55 -04:00
871460016d
makefile: added
2015-04-01 16:27:54 -04:00
c0a4c6e046
makefile: added
2015-04-01 16:27:52 -04:00
5a5ffb7745
makefile: added
2015-04-01 16:27:51 -04:00
54ee0a0273
makefile: added
2015-04-01 16:27:50 -04:00
3dbbb4e5bb
makefile: added
2015-04-01 16:27:49 -04:00
566e8d7fd3
makefile: added
2015-04-01 16:27:47 -04:00
500f71af2f
makefile: added
2015-04-01 16:27:46 -04:00
4e7538fc8b
makefile: added
2015-04-01 16:27:45 -04:00
13a40af558
makefile: added
2015-04-01 16:27:44 -04:00
36b629dab1
makefile: added
2015-04-01 16:27:42 -04:00
856220e9e9
makefile: added
2015-04-01 16:27:41 -04:00
43f5025ecd
makefile: added
2015-04-01 16:27:40 -04:00
5b18d12c23
makefile: added
2015-04-01 16:27:39 -04:00
f20ab424f7
makefile: added
2015-04-01 16:27:37 -04:00
4ab17615ce
makefile: added
2015-04-01 16:27:36 -04:00
234d4ae7f3
makefile: added
2015-04-01 16:27:35 -04:00
55406b7a61
makefile: added
2015-04-01 16:27:34 -04:00
6cff03390c
makefile: added
2015-04-01 16:27:32 -04:00
a97fc603f8
makefile: added
2015-04-01 16:27:31 -04:00
35205c43a1
makefile: added
2015-04-01 16:27:30 -04:00
1b5737968a
makefile: added
2015-04-01 16:27:29 -04:00
6ac43fe516
makefile: added
2015-04-01 16:27:27 -04:00
c2e626d0b6
axi_hdmi_tx: es split
2015-04-01 15:08:24 -04:00
3bca324c33
hdmi_rx: 64bit + es split
2015-04-01 14:25:55 -04:00
56165b89f7
hdmi_rx: 64bit + es split
2015-04-01 14:25:49 -04:00
01d0b495ec
hdmi_rx: 64bit + es split
2015-04-01 14:25:45 -04:00
d4763fe356
hdmi_rx: 64bit + es split
2015-04-01 14:25:41 -04:00
11d94b736a
util_gmii_to_rgmii: Added to dev branch
2015-04-01 17:22:49 +03:00
ae26c7817e
Remove util_sync_reset
...
The util_sync_reset peripheral hasn't been used in a while and will not be
used in new projects. So remove it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-01 14:46:41 +02:00
fd7a423f74
axi_dmac: Reset data stream resize blocks when disabled
...
When the DMA controller gets disabled in the middle of a transfer it is
possible that the resize block contains a partial sample. Starting the next
transfer the partial sample will appear the begining of the new stream and
also cause a channel shift.
To avoid this make sure to reset and flush the resize blocks when the DMA
controller is disabled.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-01 14:18:34 +02:00
2d7bae2ba6
axi_mc_controller: Added delay module
2015-04-01 12:22:20 +03:00
de12184038
axi_mc_speed: Updated for motor control revision 2
2015-04-01 11:43:22 +03:00
d5fa0071bd
axi_mc_current_monitor: Updated for motor control revision 2
2015-04-01 11:42:28 +03:00
6ee66df41e
axi_mc_controller: Updated for motor control revision 2
2015-04-01 11:41:33 +03:00
4b1d9fc86b
axi_dmac: Modified in order to avoid vivado crash
2015-04-01 11:39:25 +03:00
e116822059
imageon_zc706: Updates and fixes
...
+ sync the sof to the dma_de signal
+ hdmi_rx_dma is connected to the HP1
+ fix syncronization signal in the CSC module
+ hdmi_rx_clk is asynchronous
2015-03-27 18:57:32 +02:00
0e1a60e8b7
axi_dmac: Brought up the transfer request signal for the dest_fifo and dest_axi_stream interface.
2015-03-26 12:20:32 +02:00
6ee9b3a1e2
util_wfifo: Fixed reset
2015-03-25 15:34:21 +02:00
552d9b41f7
imageon: updates
2015-03-24 15:08:48 -04:00
b29e97f985
hdmi_rx: imageon updates
2015-03-24 15:08:48 -04:00
ffe410b2dd
hdmi_rx: imageon updates
2015-03-24 15:08:48 -04:00
09bb184505
hdmi_rx: imageon updates
2015-03-24 15:08:48 -04:00
f92011f72d
hdmi_rx: imageon updates
2015-03-24 15:08:48 -04:00
5d50d38c66
hdmi_rx: imageon updates
2015-03-24 15:08:48 -04:00
80c2a5a45d
axi_hdmi_rx: General clean up
2015-03-23 12:39:26 +02:00
8f5551718e
axi_fifo2s: false paths on up_xfer_toggle
2015-03-19 16:33:14 -04:00
7e15fd9e5b
util_upack: Fixed ip
2015-03-19 16:22:12 +02:00
bc04e5a4ce
axi_i2s_adi: Fixed pins directions
2015-03-12 17:22:52 +02:00
8dfcbdfd48
gt_channel/gt_common: simulation parameter warning fix
2015-03-06 12:36:07 -05:00
57e1f0e334
gt_channel/gt_common: simulation parameter warning fix
2015-03-06 12:36:03 -05:00
2d01955042
up_gt: change version dfe/lpm support
2015-03-05 09:47:16 -05:00
6995f63134
Add version check to adi_ip.tcl too.
2015-03-05 11:55:09 +02:00
1613f7fb41
cftl_cip: Add util_pmod_fmeter IP to library
...
Frequency meter IP for CN0332.
2015-02-23 17:20:12 +02:00
65bda6505e
axi_dmac: Correctly handle shutdown for the request splitter
...
We need to make sure to not prematurely de-assert the s_valid signal for the
request splitter when disabling the DMAC. Otherwise it is possible that
under certain conditions the DMAC is disabled with a partially accepted
request and when it is enabled again it will continue in an inconsistent
state which can lead to transfer corruption or pipeline stalls.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:23 +01:00
731e1c0996
axi_dmac: Use internal enable signal for the request generator
...
All components should use the internal 'do_enable' signal instead of the
external 'enable' signal. The former correctly incorporates the shutdown
sequence and does not get asserted again until the shutdown has been
completed. Using the external signal can cause problems when it is disabled
and enabled again in close proximity.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:23 +01:00
582ea06918
axi_dmac: request_generator: Stop generating requests when disabled
...
Currently when the DMAC gets disabled the request_generator will still
generate all remaining burst requests for the currently active transfer.
While these requests will be ignored by the source and destination component
this can still take a fair amount of time for long transfers.
So just stop generating burst requests once the DMAC is being disabled.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:23 +01:00
aa594e15f3
axi_dmac: fifo_inf: Handle overflow and underflow correctly
...
Refactor the fifo_inf modules to always correctly generate the underflow and
overflow status signals. Before it was possible that in some cases they
were not generated when they should have been.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:21 +01:00
6edcaa478a
adi_ip: updates for 2014.4
2015-02-19 11:11:39 -05:00
9cdec38532
gt- report device type
2015-02-17 11:43:57 -05:00
2442b6e929
gt- report device type
2015-02-17 11:43:50 -05:00
fccadcec31
jesd_gt: lpm/dfe programmable
2015-02-13 11:33:25 -05:00
de043ce130
gt_channel: lpm/dfe programmable
2015-02-13 11:33:04 -05:00
870ebdb562
up_gt: support lpm mode
2015-02-12 16:21:11 -05:00
1e7c9a3924
gt_es: support lpm mode - 2/2
2015-02-12 16:20:43 -05:00
0a8e6f62ef
gt_es: support lpm mode - 1/2
2015-02-12 15:15:18 -05:00
9e2e2ef44e
xfer-logic: stretch toggles to allow capture
2015-02-06 22:15:16 -05:00
e9231c8f36
xfer-logic: stretch toggles to allow capture
2015-02-06 22:15:14 -05:00
518d842af9
upack: initial commit
2015-02-06 15:15:33 -05:00
d02c21b426
util_pmod_adc: General update
...
Redesign the state machine, rename constant and variable names, add notes and description.
2015-02-04 14:49:16 +02:00
96899313d8
axi_dmac: Fix constraint
...
Change the constraint file extension to .xdc, no more need for the .tcl workaround.
2015-01-23 18:51:25 +02:00
b10ba49425
axi_dmac: Fix constraint related issue
...
Tcl command "if" is not supported by Vivado XDC, therefore the tool throw some critical warnings, and does not
apply the constraints, which can cause timing violations at case of some carriers.
The following solution is much more compact and is supported by the XDC, and more importantly prevents
unwanted critical errors and timing violations.
2015-01-23 18:44:17 +02:00
d5bd485624
axi_dmac: Fix eot issue under 2014.4
...
Vivado 2014.4 is too greedy, when it needs to optimize. See more about the issue here: https://ez.analog.com/thread/48214
The response_dest_resp is unused, so not save to concatenate with a valid signal like the eot.
2015-01-23 18:39:33 +02:00
659e0cca4e
cftl_cip: Initial check in.
...
Project cftl_cip supports the following Circuits from the Lab pmods:
+ EVAL-CN0350-PMDZ
+ EVAL-CN0335-PMDZ
+ EVAL-CN0336-PMDZ
+ EVAL-CN0337-PMDZ
Note: Additional testing needed!
2015-01-23 18:29:32 +02:00
5a1819ed6e
fifo2s: qualify last with valid
2015-01-15 15:42:10 -05:00
debbe31713
Merge remote-tracking branch 'origin/master' into dev
2015-01-09 11:12:56 -05:00
63633a0fa5
ad9739a: constraints
2015-01-08 10:25:45 -05:00
ed73a9d1cf
ad9739a: updated to ad9739a
2015-01-08 10:25:15 -05:00
14df46c193
library: Initial commit of axi_hdmi_rx ip core
...
Status unknown, NOT tested.
2015-01-08 16:58:56 +02:00
9f485f2f4e
common: Add register map module for HDMI receiver.
2015-01-08 12:24:47 +02:00
161e6cc70d
common: Add color space sampling and color space conversion modules
...
This two module are used by the HDMI receiver.
2015-01-08 12:24:46 +02:00
ad4b4f64d0
ad9739a: ad9122 copy
2015-01-07 15:36:02 -05:00
3a4d765a2b
up_clkgen: reading typo
2015-01-07 14:02:39 -05:00
b65bcab8d6
up_clkgen: reading typo
2015-01-07 13:58:43 -05:00
5f93c859b5
util_rfifo: renamed ports to make vivado happy
2015-01-06 16:16:42 -05:00
8056574bae
util_wfifo: renamed ports to make vivado happy
2015-01-06 16:16:25 -05:00
0291bb3bf7
util_rfifo: port name fixes & doc.
2015-01-06 16:15:51 -05:00
36b041ccc0
util_wfifo: port name fixes & doc.
2015-01-06 16:15:42 -05:00
ee0912eb6a
ad9361: make 2t2r external for mw
2015-01-05 10:54:23 -05:00
c3529f112f
up_gt: move status to up clock
2014-12-19 13:00:27 +02:00
f4774d6f98
fifo2s: false path typo on source signals
2014-12-19 13:00:13 +02:00
1d6ea64d04
up_gt: move status to up clock
2014-12-16 08:48:13 -05:00
16f64a75d6
fifo2s: false path typo on source signals
2014-12-15 13:00:13 -05:00
04c10abc2f
gth/gtx: share same cpll/qpll cpu settings
2014-12-11 11:18:48 -05:00
c4152627f0
plddr3: Sync adc_wcnt_int to adc_wr and fix adc_dwr pulse width
...
The adc_wcnt_int must be synchronized to adc_wr. The adc_dwr signal pulse width was to long,
it needs to be just one adc_clk cycle.
2014-12-09 13:59:19 +02:00
19732d89fb
plddr3: Fix the adc_dwr pulse width
...
The adc_dwr signal pulse width was to long, need to be just one adc_clk cycle.
2014-12-09 13:51:00 +02:00
6aad2fbbb2
axi_hdmi_tx: Fixed typo in altera related core
2014-12-09 10:19:03 +02:00
6f8c259961
axi_hdmi_tx: Fixed typo in altera related core
2014-12-09 09:56:14 +02:00
a70d27c094
axi_mc_speed: updated core to latest axi interface implementation
2014-12-05 11:53:11 +02:00
26f58914e2
axi_mc_current_monitor: updated core to latest axi interface implementation
2014-12-05 11:53:06 +02:00
7e8e1e4fd0
axi_mc_controller: updated core to latest axi interface implementation
2014-12-05 11:52:59 +02:00
ea1a50c985
axi_mc_speed: updated core to latest axi interface implementation
2014-12-05 11:46:20 +02:00
0d2888a5a6
axi_mc_current_monitor: updated core to latest axi interface implementation
2014-12-05 11:45:37 +02:00
21591dc485
axi_mc_controller: updated core to latest axi interface implementation
2014-12-05 11:43:59 +02:00
6197563506
up_axi: Fix up_raddr/up_waddr port width
...
Make sure that the port declaration width matches with the reg declaration
later on.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-01 13:45:45 +01:00
8cc9adfc49
up_axi: Fix up_raddr/up_waddr port width
...
Make sure that the port declaration width matches with the reg declaration
later on.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-01 13:22:28 +01:00
afddc45ba4
library/ccat: initial commit
2014-11-25 12:59:51 -05:00
196e8b119c
library/bsplit: initial commit
2014-11-25 12:59:50 -05:00
403f8c0631
util_cpack: ipi doesn't like local params
2014-11-21 15:32:13 -05:00
3b500bafcc
util_cpack: add port controls on ipi
2014-11-21 15:32:12 -05:00
5ca2944b70
library/util_cpack: initial checkin
2014-11-21 15:32:10 -05:00
42874bfe81
prcfg_library: Major update
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Get rid of the QPSK symbol wrapper for now. The DMA data path is using the 2 LSB bits.
2014-11-18 10:05:52 +02:00
a4724f8396
es: added kcu105 gth
2014-11-17 09:55:12 -05:00
b1c91fac92
es: added kcu105 gth
2014-11-17 09:55:10 -05:00
fd305f2eff
es: added kcu105 gth
2014-11-17 09:55:09 -05:00
6dd1226696
axi_ad9643: Fixed constraint file
2014-11-17 12:12:09 +02:00
8831d9dbd7
axi_ad9122: fixed constraint file
2014-11-17 12:11:20 +02:00
2744d0cb37
util_wfifo: Update to implement flip flops
2014-11-17 12:10:21 +02:00
41ffc66c26
fifo2s: removed m interface
2014-11-13 15:00:03 -05:00
8761db438e
axi_fifo2f: common interface with fifo2s
2014-11-12 15:15:32 -05:00
925e966eb6
axi_fifo2s: fifo full replaced with ready
2014-11-12 14:43:47 -05:00
5fc4f1b000
axi_fifo2s: buswidth fix
2014-11-12 14:43:46 -05:00
d204a7c2b7
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:44 -05:00
e7cec7171e
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:43 -05:00
4381f20a6a
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:42 -05:00
9f2dbad539
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:41 -05:00
e683b5868e
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:40 -05:00
81b4cd532d
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:38 -05:00
888ab888d2
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:37 -05:00
f8e7796592
axi_jesd_gt: Fix lane number parameters
2014-11-12 17:43:32 +02:00
bf62665c56
prcfg_qpsk: Add Simulink model
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Matlab version used: R2014a, HDL Coder 3.3
2014-11-12 15:44:38 +02:00
64ec633438
gt: asymmetric no of lanes
2014-11-11 08:54:24 -05:00
cb15567a56
ad6676: added
2014-11-10 13:36:07 -05:00
c6df568a00
Revert "ad_interrupts: Initial check in."
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This reverts commit b254380338
2014-11-06 12:16:52 +02:00
b11d80ed98
ad_rst: changed to dual stage
2014-11-05 16:48:02 -05:00
74ec396b27
ad_rst: ultrascale -dual stage
2014-11-05 16:47:41 -05:00
d69ccebbde
ad9234: full 16bit samples
2014-11-05 11:59:08 -05:00
403fe1b373
wfifo: read only if ready is asserted
2014-10-31 13:05:17 -04:00
38652b1c3e
axi_ad9643: Added constraint file
2014-10-31 17:57:47 +02:00
Lars-Peter Clausen
Rejeesh Kutty
Adrian Costina
Istvan Csomortani