e086f5eb9f
axi_ad9361: Updated core with the new up_adc_common register set
2014-10-27 19:26:40 +02:00
de33722470
up/constr: independent read/write and local constraints
2014-10-02 14:35:59 -04:00
3162540b03
axi_ad9361: Remove the Altera toplevel wrapper
...
By setting the AXI controler interface type from axi4 to axi4lite we can use
the normal toplevel file with only a simple modification to add the awprot
and arprot signals.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:29:13 +02:00
41cc92ef49
Remove BASEADDR/HIGHADDR parameters
...
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
a4b9b1254a
axi_ad9361/axi_dmac: Fix altrea AXI wrapper rid/wid handling
...
We must make sure that the response ID is the same as the request ID when we
accepted the request. Otherwise we might respond with the wrong ID and the
system will lockup.
Also set rlast to 1 instead of 0.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:05:06 +02:00
50faf0c53a
Remove executable flags from non-exectuable files
2014-09-09 15:05:06 +02:00
59759a8ab3
c5soc: working hdl version
2014-07-24 20:51:41 -04:00
6346017763
c5soc: changed to alt_lvds - 250M is too high for cyclone v
2014-07-24 20:51:40 -04:00
c0e31aa6c2
daq2: latest hardware
2014-07-21 09:06:57 -04:00
2955b9db78
fifo2s: flush if no request, c5soc: 14.0
2014-07-15 16:25:33 -04:00
39ac29bb01
AD9361: Altera, modified address width so that all registers are accessible
...
Modified qsys project with the new address span
2014-07-08 10:41:51 +03:00
a388ccab0a
fmcomms2/c5soc: initial checkin
2014-07-02 14:56:00 -04:00
b6052773b7
added adc/dac gpio registers
2014-06-27 14:45:58 -04:00
10a7804e14
ad9361: altera wrapper updates
2014-06-25 15:26:06 -04:00
985ace533e
ad9361: remove unused modules
2014-06-24 14:26:40 -04:00
e650253013
library: register map changes and for mathworks
2014-06-24 14:22:05 -04:00
bef6a9c32c
axi_ad9361: Split dma data into individual channels for both ADC and DAC
2014-06-07 17:15:31 +03:00
5b5bca400f
ad9361: added adc loopback
2014-05-27 14:47:59 -04:00
842cd98b61
ad9361: adc loopback option
2014-05-27 12:15:02 -04:00
3aed3ba71c
axi_ad9361: fmcomms5 changes
2014-05-19 12:41:12 -04:00
a007add714
iqcorrection: missing input signals fix
2014-05-09 11:17:50 -04:00
1d50489870
ad9361: ml605 updates
2014-05-05 11:03:57 -04:00
570ec26798
FMCOMMS2: Added sync option
2014-04-11 18:14:48 +03:00
99ef34936f
Merge branch 'master' of https://github.com/analogdevicesinc/hdl
2014-04-11 18:14:08 +03:00
c73390b6c9
axi_ad9361: Intermediary check in for altera porting
...
This is work in progress. It will not work as it is
2014-04-11 17:40:34 +03:00
5aac9d7288
FMCOMMS2 added sync option
...
Added signals to allow synchronisation of multiple AD9361.
2014-04-10 10:46:42 +03:00
25f416e46f
dds output is reset if disabled
2014-03-31 10:01:49 -04:00
ad491e92ab
changed pcore version and made it local (top shouldn't override)
2014-03-14 12:02:16 -04:00
580808e146
axi_ad9361: added
2014-03-11 20:01:55 -04:00
Adrian Costina
Rejeesh Kutty
Lars-Peter Clausen
ATofan
U-ANALOG\ACostina