Commit Graph

13 Commits (c3aa014105f4ded0b9887c88b8fe5834dbc47218)

Author SHA1 Message Date
Iulia Moldovan 0590a4046c Add copyright & license for all files needing ADI JESD specific license
* Added every year when the file was edited, with comma
 * Range if it's consecutive years

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-09-07 10:45:49 +03:00
Ionut Podgoreanu 5c86c15ff3 library/jesd204: Add support for a gearbox ratio in which the TPL width is smaller than the PHY interface 2022-08-25 12:35:42 +03:00
Iacob_Liviu 482f0489a3 scripts: Merge adi_env.tcl into a single file
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
Filip Gherman 929f80cd31 library/jesd204: Updated jesd to support more lanes
Modified the maximum number of supported lanes up to 32 lanes for every JESD layer

Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-08-04 13:10:53 +03:00
Istvan Csomortani f0027faf88 adi_jesd204: Add support of 16 lanes 2021-07-27 10:28:48 +03:00
stefan.raus 4a772265a9 Update Quartus Prime version from 19.3.0 to 20.1.0
adi_project_intel.tcl: Change quartus version to 20.1.0.
library: Set qsys version so that IP instances won't require a specific version.
2021-03-08 11:29:33 +02:00
Laszlo Nagy dd58759cd8 jesd204: Intel: NP12 support
Dual clock mode is introduced in link layer to support different
datapath widths on the transport layer than on physical layer.

- Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b
- Device clock : Link clock * input data path width / output datapath width

Supports four clock configurations, single or dual clock mode with or
without external device clock.

The configuration interface reflects the dual clock domain.
2021-02-05 15:24:15 +02:00
Matt Blanton 400c3927f7 jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement
Add support to JESD204 RX and TX core for 8-byte 8b/10b link mode,
and frame alignment character replace/insert with or without scrambling.
Add support for xcelium simulator to jesd204/tb
Increased cores minor version.
2021-02-05 15:24:15 +02:00
Laszlo Nagy f2060e27be jesd204_tx: add output pipeline stage
In order to help timing closure on multi SLR FPGAs add a pipeline stage
between the link layer and physical layer. This will add a fixed amount
of delay to the overall latency.
2020-02-07 09:02:46 +02:00
Istvan Csomortani 5329458a62 library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani da03572b32 jesd204_tx: Add dynamic multi-link support
A multi-link is a link where multiple converter devices are connected to a
single logic device (FPGA). All links involved in a multi-link are synchronous
and established at the same time. For a TX link this means that the FPGA receives
multiple SYNC signals, one for each link. The state machine of the TX link
peripheral must combine those SYNC signals into a single SYNC signal that is
asserted when either of the external SYNC signals is asserted.

Dynamic multi-link support must allow to select to which converter devices on
the multi-link the SYNC signal is propagated too. This is useful when depending
on the use case profile some converter devices are supposed to be disabled.

Add the cfg_links_disable[0x081] register for multi-link control and
propagate its value to the TX FSM.
2018-05-03 19:37:35 +03:00
Istvan Csomortani 09ff1f3a77 jesd204: Fix file names
All the file names must have the same name as its module. Change all the
files, which did not respect this rule.
Update all the make files and Tcl scripts.
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 2d896c0729 jesd204: Add Altera/Intel IP support
Add Qsys IP scripts as well as SDC constraint files for the ADI JESD204
peripherals. This allows them to be instantiated and used on Altera/Intel
platforms.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:09:42 +02:00