zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
6,413 Commits
1 Branch
0 Tags
23 MiB
Commit Graph

10 Commits (c3aa014105f4ded0b9887c88b8fe5834dbc47218)

Author SHA1 Message Date
Iulia Moldovan c9a7d4d927 Add copyright and license to .tcl, .ttcl files 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-07-25 15:22:26 +03:00
Iacob_Liviu 482f0489a3 scripts: Merge adi_env.tcl into a single file 
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
 2022-08-08 13:52:54 +03:00
Nick Pillitteri c1721e18dd account for ADI_VIVADO_IP_LIBRARY global variable when adding subcores 2022-03-24 16:29:49 +02:00
Istvan Csomortani 363494ab9c library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 3f7f2f9c9f util_adcfifo: Fix the address generation and read logic 2019-05-28 08:48:16 +03:00
Istvan Csomortani 79e21a361c util_adcfifo: Synchronize the ad_rst and use it as a synchronous reset 
This improvement will solve a couple of [DRC REQP-1839] warning:

"The RAMB36E1 has an input control pin * which is driven by a register * that has
an active asynchronous set or reset. This may cause corruption of the memory
contents and/or read values when the set/reset is asserted and is not analyzed
by the default static timing analysis. It is suggested to eliminate the use of
a set/reset to registers driving this RAMB pin or else use a synchronous reset
in which the assertion of the reset is timed by default."
 2018-08-21 11:42:48 +03:00
Adrian Costina 74b922f9f8 axi_*: Infer clock and reset signals of an IP 
A clock sink must be connected to clock source, and a reset sink to
reset source, otherwise the tool will throw a synthesis warning.
By properly inferring all the reset and clock signals of an IP, we can
get rid of unwanted warning messages.

The following IPs tcl script was updated:
  - axi_ad9434
  - axi_hdmi_tx
  - util_cpack
  - util_adxcvr
  - axi_ad6676
  - axi_ad9625
  - axi_ad9379
  - axi_ad9265
  - util_tdd_sync
  - util_rfifo
  - util_wfifo
  - axi_ad9361
  - axi_ad9467
  - util_upack
  - axi_dacfifo
  - axi_ad9152
  - axi_ad9680
  - util_clkdiv
  - axi_ad9122
  - axi_ad9684
  - axi_mc_speed
  - axi_mc_current_monitor
  - axi_mc_controller
  - util_gmii_to_rgmii
  - util_adxcvr
  - axi_ad9379
  - axi_hdmi
  - library
  - axi_fmcadc5_sync
  - util_adcfifo
  - util_mfifo
  - axi_jesd204_rx
  - axi_jesd204_tx
  - axi_ad9361
  - axi_adxcvr_ip
 2018-04-11 15:09:54 +03:00
Istvan Csomortani c1bdfca4c3 library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file 
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-06-26 11:07:10 +02:00
Rejeesh Kutty 86a70b3054 adcfifo: added 2015-04-07 15:43:02 -04:00