Iulia Moldovan
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c9a7d4d927
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Add copyright and license to .tcl, .ttcl files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
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2023-07-25 15:22:26 +03:00 |
Iacob_Liviu
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482f0489a3
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scripts: Merge adi_env.tcl into a single file
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
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2022-08-08 13:52:54 +03:00 |
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LIacob106
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076e81a17c
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library: Add link to wiki for IPs
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2021-10-25 10:44:53 +03:00 |
Istvan Csomortani
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363494ab9c
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library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl
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2019-06-29 06:53:51 +03:00 |
Adrian Costina
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74b922f9f8
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axi_*: Infer clock and reset signals of an IP
A clock sink must be connected to clock source, and a reset sink to
reset source, otherwise the tool will throw a synthesis warning.
By properly inferring all the reset and clock signals of an IP, we can
get rid of unwanted warning messages.
The following IPs tcl script was updated:
- axi_ad9434
- axi_hdmi_tx
- util_cpack
- util_adxcvr
- axi_ad6676
- axi_ad9625
- axi_ad9379
- axi_ad9265
- util_tdd_sync
- util_rfifo
- util_wfifo
- axi_ad9361
- axi_ad9467
- util_upack
- axi_dacfifo
- axi_ad9152
- axi_ad9680
- util_clkdiv
- axi_ad9122
- axi_ad9684
- axi_mc_speed
- axi_mc_current_monitor
- axi_mc_controller
- util_gmii_to_rgmii
- util_adxcvr
- axi_ad9379
- axi_hdmi
- library
- axi_fmcadc5_sync
- util_adcfifo
- util_mfifo
- axi_jesd204_rx
- axi_jesd204_tx
- axi_ad9361
- axi_adxcvr_ip
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2018-04-11 15:09:54 +03:00 |
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Adrian Costina
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b9c94f63a5
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util_extract: Initial commit
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2017-01-31 16:26:05 +02:00 |