Update clean command to delete also files generated by simulation,
from 'tb' folders, covering cases for Xsim and ModelSim simulators.
Signed-off-by: stefan.raus <stefan.raus@analog.com>
* Before, adc_valid was for the previous sample. This said that
at the second rising edge of clk_gate - the first sample is valid,
which is not true
* Alongside with the software issue that will be solved, these fixes
will make the first 2 samples to be with valid data, otherwise the
user has to always keep in mind that the first 2 ones are invalid
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
* library/common: Ad adc_status_header, adc_crc_err and adc_crc_enable.
* library/axi_ad777x: Initial commit for Xilinx and Intel
* projects/ad777x_ardz: Initial commit for ZedBoard and DE10Nano
When capture length is not programmed the DMA will interrupt the
transfer once it received all the samples he was set in its descriptor,
this case must be handled by resetting the read process and returning
an end of transfer (eot) to the data offload control logic.
Tx path was gated by the FSM also in bypass mode. This must be avoided
since the bypass mode should be independent of the FSM.
Write to bypass fifo only when bypass is enabled
* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
On architectures with ports that support cache coherency, the AWCACHE
signal must be set to indicate that transactions are cached. This patch
adds a parameter allowing AWCACHE to be set on an AXI4 destination port.
Deprecate unused parameters.
Change to MEM_SIZE_LOG2, to support only power of 2 storage sizes for
now. However in the future we might want to add support for non pow2
sizes so register map is not changed.
Change transfer length to -1 value to spare logic.
Change FIFO interface to AXIS to have backpressure, this allows the
implementation of data movement logic in the storage unit and let the
FSM handle high level control an synchronization and control the storage
unit through a control interface.
Refactor FSM to have preparation states where slow storages can be
configured and started ahead of the data handling.
Make bypasss FIFO optional since in some cases causes timing failures
due the missing output register of the memory. This can be targeted in
a later commit.
Hook up underflow/overflow to regmap useful in case of external memory
where rate drops due misconfiguration can be detected.
Cleanup for verilator.
Scripting:
Add HBM and DDR external memory support using util_hbm IP
Replace asym_block_ram with util_do_ram IP
This IP replaces the ad_mem_asym module as storage element for the data
offload.
Having standard AXIS interface for data will allow
implementation of storages on UltraRAM.
This IP serves as storage interfacing element for external memories like
HBM or DDR4 which have AXI3 or AXI4 data interfaces.
The core leverages the axi_dmac as building blocks by merging an array of
simplex DMA channels into duplex AXI channels. The core will split the
incoming data from the source AXIS interface to multiple AXI channels,
and in the read phase will merge the multiple AXI channels into a single
AXIS destination interface.
The number of duplex channels is set by syntheses parameter and must be
set with the ratio of AXIS and AXI3/4 interface.
Underflow or Overflow conditions are reported back to the data offload
through the control/status interface.
In case multiple AXI channels are used the source and destination AXIS
interfaces widths must match.
This allows the external synchronization input to be driven from
asynchronous sources like a 1 PPS signal or just signals from different
clock domains in general.
Signed-off-by: David Winter <david.winter@analog.com>
up_xfer_done should signalize when a previous control set is
transferred to the other clock domain and the current control set is latched.
If a bit from the up_data_cntrl changes, it should stay in that state until
the up_xfer_done asserts.
When using a CLK_RATIO > 1 the first n samples(n=CLK_RATIO) after sync, are
noisy. This is because the phase accumulator data is passed to the phase to
amplitude converter, during the phase synchronization step.
This patch fixes an issue where the pulse width is only updated two
periods after the current one.
Signed-off-by: David Winter <david.winter@analog.com>
Current implementation is correct only for datapath width of 8.
The buswidth of latency measurement inside a beat has a fixed width (3 bits)
for each lane that must be taken in account when computing the total latency.
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
Data to DMA/system memory must be presented in widths of multiple of 8 bits,
however this padding is not optimal if is done in the transport layer
since this will affect the DAC/ADC FIFO or offload storage.
This utility block adds or removes padding from sample stream in case the
sample with is not multiple of 8 bits, and can be placed between the DMA
and FIFO/Offload blocks.
On large projects with multiple channels the databus on the FIFO/AXI
stream interface can get wider that 1024 bits.
This commit allows a wider range for all the interfaces,
in case for the memory mapped interfaces where the range is 32-1024 the
user selects a bus width out of range that will be handled by the IPI.
PopPaul2021
stefan.raus
Iulia Moldovan
Laszlo Nagy
Ionut Podgoreanu
LIacob106
Filip Gherman
Adrian Costina
Benjamin Menkuec
Mathias Tausen
David Winter
AndrDragomir
Nick Pillitteri
alin724
alin724
AndreiGrozav
sergiu arpadi
Nicola Corna
Dan Hotoleanu