d7a6b5e6d0
fmcomms2/ml605: compilation fixes
2014-12-09 14:31:11 -05:00
d57b6b01c6
fmcomms2/ml605: compilation fixes
2014-12-09 14:31:10 -05:00
d5422c2ecc
fmcomms2: Zed, fixed iic multiplexer ad_iobuf connections
2014-11-28 14:17:09 +02:00
199e86d715
fmcomms2: Added iic_fmc_intr to the zed top file
2014-11-26 11:47:16 +02:00
03751827cb
fmcomms2: Updated vc707 project
...
- updated constraints
- updated interrupts
- used ad_iobuf
- added linear_flash
2014-11-26 11:47:06 +02:00
40c5816bd7
fmcomms2: Updated mitx045 project. Updated constraints. Updated interrupts
2014-11-26 11:46:53 +02:00
ad08c62b36
fmcomms2: Updated zc702 project. Updated interrupts. Updated constraints
2014-11-07 14:01:55 +02:00
4e11e39956
fmcomms2: Updated zed project
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- Updated interrupt system to the latest implementation
- Fixed constraints
2014-11-07 13:59:46 +02:00
962df53946
fmcomms2: Updated kc705 project to vivado 2014.2.
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- Updated interrupt system to the latest implementation
- Fixed constraints
- Used ad_iobuf
2014-11-07 13:58:40 +02:00
db18ed4af2
fmcomms2: Updated ac701 project to vivado 2014.2.
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- Updated interrupt system to the latest implementation
- Fixed constraints
- Used ad_iobuf
2014-11-07 13:56:00 +02:00
7e2a9ce569
fmcomms2: Updated base design interrupt system for microblaze
2014-11-07 13:54:43 +02:00
6fac294b6f
fmcomms2: Updated zc706 project to new interrupt system
2014-10-31 14:15:29 +02:00
d04a545a41
fmcomms2: updated zc706 project with new constraint style
2014-10-27 19:27:36 +02:00
17675863e0
all_projects: Fix the interrupt connections to preserve IRQ layout
2014-10-22 11:48:08 +03:00
4b8720b551
fmcomms2_zc706: Remove top level constraints
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Remove all the unnecessary top level constraint definitions.
2014-10-20 13:25:01 +03:00
f528873fa9
fmcomms2: Add an additional SPI interface for up/down converter board
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Supported carriers are: ZC706, ZC702 and Zed.
2014-10-10 18:47:07 +03:00
ca4c961891
fmcomms2: Use ad_iobuf instance on system_top
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Use ad_iobuf instance on system top, instead of separate IOBUF instances.
2014-10-10 18:45:39 +03:00
e21d26e456
fmcomms2: Cosmetic changes
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Get rid of unwanted whitespaces.
2014-10-10 18:25:17 +03:00
fe8a076b2e
fmcomms2: Cosmetic changes on *_bd.tcl script
2014-10-10 17:06:32 +03:00
7a9e694446
fmcomms2: Connect DMA directly to the HP ports
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The DMA controller is able to send AXI3 compatible requests, no need to add
a interconnect for protocol conversion in between the DMA controller and the
HP port.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:14 +03:00
87047fd83e
fmcomms2: Set dac_unpack channels to 4
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There are only 4 DAC channels in the fmcomms2 design, so set the number of
channels of the dac_unpack core to 4. This slightly reduces resource usage
as well as reducing the DMA alignment requirement from 128bit to 64bit. The
later value is what existing applications expect the alignement requirement
to be.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:06 +03:00
2da395926e
fmcomms2: Upgrade project to 2014.2
2014-10-09 18:54:33 +03:00
7e40f99fe9
fmcomms2: Improved constraints for ac701 and zc702. Fixed common design so that ILA works correctly on microblaze based systems
2014-09-23 22:28:27 -04:00
f43b5d707e
fmcomms2: Reduced clock frequency for ILA to meet timing for ZED
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Modified ZED constraints to 250 MHz for the clock from AD9361
2014-09-16 16:08:28 -04:00
d8651cdd2e
fmcomms2: c5soc: Set dac_util_unpack number of channels to 4
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We only do have 4 channels in this design. Reducing the number of supported
channels for the dac_util_unpack core to 4 from 8 lowers the DMA alignment
requirement from 128bit to 64bit. We need this since applications only
expect a DMA alignment requirement of 64bit.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-12 16:15:12 +02:00
ecc498313c
fmcomms2: c5soc: Connect ADC, DAC and VGA DMA to different bridge interconnects
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We have enough bridge interconnect to give each DMA its own, so use them.
This makes sure that they do not interfere with each others transfers to
much. The SDRAM controller side of the FPGA2SDRAM bridges FIFO runs at a
much faster frequency then what we are able to use in the fabric. So its
better to do the arbitration on that side of the bus to make sure that we
can utilize the buses in the FPGA fabric to the maximum for each DMA core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-12 16:14:07 +02:00
61f21a17b3
fmcomms2:c5soc project upgraded with util_dac_unpack
2014-09-11 15:13:09 -04:00
4c1c50788e
fmcomms5: c5soc: Fix typo
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 17:15:10 +02:00
c7989925c5
fmcomms2: c5soc: Add false path between 50MHz and VGA PLL clock
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Otherwise we get timing errors for the reset signal that is generated in the
50MHz clock domain, but used in the VGA PLL clock domain.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:05:06 +02:00
328205c31d
fmcomms2: c5soc: Set DMA transfer length to 24 bits
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14 bits is a bit to low and we use 24 bits everywhere else as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:05:06 +02:00
50faf0c53a
Remove executable flags from non-exectuable files
2014-09-09 15:05:06 +02:00
95c143412d
fmcomms2: Modified design to work with 4 channel util_adc_pack
2014-08-29 13:53:59 +03:00
5a42c10233
projects/fmcomms2/c5soc: Added video output. HPS SPI was replaced by 3 Wire SPI.
2014-08-27 21:46:23 +03:00
280260e54c
c5soc: dmac separated slave and master id widths
2014-08-22 09:08:54 -04:00
6c6cab0e16
fmcomms2: ZC706 modified constraints for linux build machines
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The added constraints allow the project to successfully pass timing on some ubuntu or debian build machines.
2014-08-01 17:34:36 +03:00
7bee85423d
c5soc: removed stp/cdf files
2014-07-24 20:53:08 -04:00
59759a8ab3
c5soc: working hdl version
2014-07-24 20:51:41 -04:00
7000897031
fmcomms2, fmcomms5: updated util_adc_pack and util_dac_unpack
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The cores now support up to 8 channels, in 1, 2, 4, 8 channel active configuration
2014-07-24 19:57:22 +03:00
c0e31aa6c2
daq2: latest hardware
2014-07-21 09:06:57 -04:00
e3320c43cb
fmcomms2/c5soc: programmer file
2014-07-21 09:06:55 -04:00
9b9e0c6a56
fmcomms2/c5soc: signal tap
2014-07-21 09:06:54 -04:00
2955b9db78
fifo2s: flush if no request, c5soc: 14.0
2014-07-15 16:25:33 -04:00
39ac29bb01
AD9361: Altera, modified address width so that all registers are accessible
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Modified qsys project with the new address span
2014-07-08 10:41:51 +03:00
10c21a343a
fmcomms2/c5soc: Fixed the spim0_ss_in_n value.
2014-07-08 10:07:31 +03:00
c53b257ab1
fmcomms2/c5soc: Fixed the MOSI and MISO pin assignments.
2014-07-07 22:28:25 +03:00
a388ccab0a
fmcomms2/c5soc: initial checkin
2014-07-02 14:56:00 -04:00
9a08189b93
c5soc: initial a5soc copy
2014-07-01 13:09:38 -04:00
ba7955c531
fmcomms2: register map modifications
2014-06-26 10:09:03 -04:00
bef6a9c32c
axi_ad9361: Split dma data into individual channels for both ADC and DAC
2014-06-07 17:15:31 +03:00
2837d788a6
mitx045: Added I2S core to the base design
2014-06-06 17:53:47 +03:00
Rejeesh Kutty
Adrian Costina
Istvan Csomortani
Lars-Peter Clausen
dbogdan