49ef9a589b
axi_ad5766: Fix parameter name for up_dac_common
2017-04-27 13:55:16 +03:00
8aa8d3a0e5
ad5766_sdz/zed: Fix i_iobuf_reset width
2017-04-27 11:28:26 +03:00
4e15a21b79
spi_engine_interconnect: Delete dependency defined for S1_CTRL interface
...
The S1_CTRL interface is not dependent of the number of SDI lines.
2017-04-27 11:28:25 +03:00
4ceed4d373
util_pulse_gen: Add Makefile
2017-04-27 11:28:25 +03:00
4836aa2179
adaq7980/zed: Update Makefile
2017-04-27 11:28:25 +03:00
18a671cdb7
spi_engine: Expose DATA_WIDTH to software
...
The value of DATA_WIDTH can be read back from register 0x44
The DATA_WIDTH will define the size of a word in a transaction.
2017-04-27 11:28:24 +03:00
801fb2281e
util_pulse_gen: The valid period is stored in pulse_period_d
2017-04-27 11:28:24 +03:00
fbccb377cc
adaq7980: Add an trigger generator for SPI offload
2017-04-27 11:28:23 +03:00
63cab50872
adaq7980_sdz: Initial commit
...
The device is interfaced with a SPI Engine, the PD lines are controlled
by GPIOs.
2017-04-27 11:28:23 +03:00
a4c422ac4c
spi_engine_execution: Define port dependencies for SDI ports
2017-04-27 11:28:21 +03:00
045cb96744
axi_spi_engine: Define ports dependencies for up_* interface
...
The up_* interface ports are active just if the MM_IF_TYPE is UP_FIFO.
2017-04-27 11:27:35 +03:00
ccc4aac505
ad5766_sdz: Fix the PIN assignment
2017-04-27 11:27:34 +03:00
8213d8a916
cn0363: Update block design
...
Configure the interconnect and offload modules inorder to activate
its interfaces. In the past, these interfaces did not have any
parameter dependencies, so this configuration were not required.
2017-04-27 11:27:33 +03:00
9cd218eb90
up_dac_common: Increase datawidth of dac_datarate
...
In case of high precision devices with just a simple SPI interface
for control and data, the effective data rate can be significatly
lower than the SPI clock, and more importantly there isn't any relation
between the two clock domain.
The rate is defined by a SOT (start of transfer) generator, which
initiates a SPI transfer. Taking the fact that the generator runs
on system clock (100 MHz), and the device can require smaller rate (in kHz domain),
the 7 bit dac_datarate register is just too small.
Therefor increasing to 16 bit.
2017-04-27 11:24:08 +03:00
a6146393be
ad5766_sdz: Fix DMA data path
2017-04-27 11:22:32 +03:00
a2c20551a2
axi_ad5766: Add Makefiles for the core
2017-04-27 11:22:31 +03:00
eba22892b8
axi_ad5766: Preserve consistent coding style
2017-04-27 11:21:15 +03:00
f5fba79a08
ad5766_zed: Add an IOBUF to the reset line
2017-04-27 11:21:14 +03:00
9de0fe56d9
ad5766: Integrate the new axi_ad5766 into the project
2017-04-27 11:21:14 +03:00
d061104a3c
util_pulse_gen: Add configuration interface for 'pulse period'.
2017-04-27 11:21:12 +03:00
825d46259b
interface: Update spi_engine_offload_ctrl definition
...
Because of the new AD5766 offload module, SDO lines are
defined as 'optional'.
2017-04-27 11:19:22 +03:00
5c5baf3abf
spi_engine: Fix CMD_FIFO_VALID generation
...
Because of the memory map interface mux, up_waddr_s should be used,
when cmd_fifo_in_valid is generated.
2017-04-27 11:19:20 +03:00
29f0ce36bb
axi_ad5766: Initial commit
...
This core can be used in conjunction with the SPI_ENGINE, will work
as an offload module, forwarding a data stream to the SPI excecution,
received from a DMA.
2017-04-27 11:16:23 +03:00
d177827224
ad5766_sdz : Fix SPI interface connection
2017-04-27 11:16:23 +03:00
fb6e0d3efb
spi_engine: Add dependency for unused interfaces
2017-04-27 11:16:19 +03:00
225d133a68
ad5766_sdz: Initial commit
2017-04-27 11:12:45 +03:00
5d6b018b2b
ad9162- add iq swap
2017-04-26 20:54:47 -04:00
85a647eda8
axi_ad9361: Fix ad_cmos_out instantiations
...
This is a patch for 3627b89
2017-04-26 10:39:54 +03:00
7cff12107e
hdlmake: Fix util_clkdiv Makefile issue. sort library master Makefile
2017-04-26 09:58:17 +03:00
cfd4e006b3
hdlmake updates
2017-04-25 15:46:26 -04:00
8fba8295f0
fmcadc5- hdl sync handling
2017-04-25 15:44:40 -04:00
68bb7ffa40
adi_board- keep port delete simple
2017-04-25 15:44:03 -04:00
804df251a6
axi_fmcadc5_sync- updates
2017-04-25 11:35:37 -04:00
81570ada75
axi_fmcadc5_sync- updates
2017-04-25 11:35:37 -04:00
c248d5ac6a
fmcadc5-sync- try sync in hdl
2017-04-25 11:35:37 -04:00
8eb65186e9
cn0363: Reorder the configuration settings of the fir filters
...
It seems that there are some dependencies between the fir compiler
cores parameters. With the old order of the parameter settings,
the tool throws the following warning:
CRITICAL WARNING: [BD 41-237] Bus Interface property TDATA_NUM_BYTES
does not match between /processing/sequencer/i_q_filtered(4)
and /processing/lpf/M_AXIS_DATA(5)
2017-04-25 17:40:09 +03:00
468965a792
altera/ad_cmos_in: Define supported DEVICE_TYPE options
2017-04-25 12:07:33 +03:00
52305f74c8
altera/ad_cmos_in|out: Delete redundant parameter
2017-04-25 12:06:33 +03:00
77eafbcccd
avl_dacfifo: Update constarint file
2017-04-25 12:03:46 +03:00
1ef3fd4668
avl_dacfifo: Fix read/write address switching
2017-04-25 12:03:22 +03:00
3627b892c3
xilinx/ad_cmos_in|out: Delete redundant parameter
...
The LVCMOS standard is a single ended IO standard. The SINGLE_ENDED
parameter is redundant in this case.
2017-04-25 11:02:35 +03:00
a6457cb54f
m2k:standalone, remove power optimizations as they are performed manually
...
- testing shows that the actual power consumtion is a bit less with them turned off
2017-04-25 10:09:55 +03:00
b92703b59f
daq2: Fix typo
2017-04-24 15:44:45 +03:00
0cfef974a6
cn0363: Fix typos and mistakes made in 0737183
2017-04-24 12:43:33 +03:00
b9bc85dd1a
daq2/zcu102: Update tcl command for IP configuration
2017-04-24 11:51:12 +03:00
871cfa7e5b
daq2/kcu105: Update tcl command for IP configuration
2017-04-24 11:50:35 +03:00
49f096dc71
daq1: Fix typo
2017-04-24 11:49:08 +03:00
4e77acf282
adv7511/kcu105: Update tcl command for IP configuration
2017-04-24 11:48:33 +03:00
4f4ca84813
axi_dacfifo: Fix Makefile
2017-04-24 11:46:29 +03:00
4007df2094
avl_dacfifo: Update constraints
2017-04-21 17:25:46 +03:00
Istvan Csomortani
Dragos Bogdan
Rejeesh Kutty
Adrian Costina