Commit Graph

3800 Commits (c4b4bdc4154d027a597e3929fda718aa7154f9e1)

Author SHA1 Message Date
Lars-Peter Clausen a0e30a2211 util_axis_fifo: Improve clock gating of registers and BRAM
Currently the BRAM and data registers in the util_axis_data are ungated
when the FIFO is ready to receive data. This good for high-performance
since it reduces the number of control signals. But it is bad from a power
point of view since it causes additional reads and writes.

Change the core gate the BRAM and data register if either the consumer is
not ready to accept data or the producer has no data to offer.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 72cdd846b0 axi_ad9963: Allow to disable the IDELAYs on the ADC data path
Not all designs need the IDELAYs. Disabling them can reduce power consumption of the system.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 09ffe42603 ad_lvds_in: Allow to disable IDELAY
The IDELAY is not always required, but it eats up power when instantiated. Allow to disable it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 45f87b46c2 ad_lvds_in: Use "SAME_EDGE" mode
Currently the IDDRs are configured in SAME_EDGE_PIPELINED mode, but then
the negative data is delayed by an additional clock cycle. This is the same
behaviour as using the IDDR in SAME_EDGE mode.

Switching to SAME_EDGE mode removes extra pipelining registers while
maintaining the same behaviour.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen c1ba57f808 m2k: Rework clocking domains
At the moment the register map fabric and DMA system memory side are
clocked by the 100MHz sys_cpu_clk. While this works fine that is a lot
faster than the clock has to run. There are only a few 100 register map
accesses per seconds at most and they are not on timing critical paths. The
penalty from clocking them at a lower rate is negligible for the overall
system performance.

The maximum clock rate for the DMAs is determined by the throughput
requirements. This is 200 Mbytes/s for the logic analyzer, pattern
generator and each of the DAC DMAs and 400 Mbytes/s for the ADC DMA.

The DMA datapath width is 64-bit so the required clock rates are 25MHz and
50MHz respectively. Some headroom is required to accommodate for occasional
bubble cycles on the data bus and the difference in reference clocks for
the converter and processing system.

The sys_cpu_clk is reduced to 27.8MHz which is fast enough for all but the
ADC DMA. For the ADC DMA a new clock domain running at 55.6 MHz is
introduced.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 2eaf931e07 m2k: Replace logic analyzer MMCM
The MMCM generating the logic analyzer clock unfortunately consumes a
disproportionately large amount of power compared to the rest of the
design.

Replace it by sourcing the logic analyzer clock from one of the Zynq FCLKs.
The IO PLL is running anyway so the power requirement is much lower.

For the time being this means we loose the ability to source the clock from
an external pin. But that feature is not supported by software at the
moment anyway. We'll bring it eventually when required.

This changes reduces power consumption by roughly 100mW.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen e616c8da0b m2k: Remove channel pack core for now
We always have both ADC channels enabled and the cpack core takes up a fair
amount of space, so remove it for now. Might come back later when we really
need it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 0e2b47e517 axi_adc_trigger: Temporarily disable trigger reporting in register map
The current implementation doesn't quite work right when the interface
clock is slower than the trigger clock and also causes timing issues.
Disable it temporarily until a proper CDC transfer is implemented.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Adrian Costina efa2d0c006 m2k: Connected adc/dac resets to decimation/interpolation cores 2017-04-18 12:17:39 +02:00
Adrian Costina be6fa287fa axi_dac_interpolate: Make dac_reset external 2017-04-18 12:17:39 +02:00
Adrian Costina 7227e74444 axi_adc_decimate: Make adc_reset external 2017-04-18 12:17:39 +02:00
Adrian Costina 500112f79b m2k: Renamed l_clk to adc_clk and rst to adc_rst 2017-04-18 12:17:39 +02:00
Adrian Costina 094872619d axi_ad9963: Separated adc/dac clock and reset 2017-04-18 12:17:39 +02:00
Adrian Costina 6a49aefb6c m2k: Updated project to use new tx path with serdes 2017-04-18 12:17:39 +02:00
Adrian Costina 9f8fd5c922 axi_ad9963: updated tx path
- removed pll for power saving, added serdes circuitry instead
2017-04-18 12:17:39 +02:00
Adrian Costina fc7f2ef11b ad_serdes_out: allow selection between DDR/SDR configuration and output single ended data 2017-04-18 12:17:39 +02:00
Adrian Costina 166a4c53d5 ad_serdes_clk: allow for single ended clock input, made BUFR_DIVIDE configurable 2017-04-18 12:17:39 +02:00
Lars-Peter Clausen b58a5c37eb m2k: Reduce AXI interconnect utilization
Use the new axi_rd_wr_combiner module to ... the read and write DMA
interfaces into a single interface. This allows the AXI interconnect
completely optimize itself away and reduce the overall resource utilization
of the project.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 71469490c6 Add a helper module to combine a AXI read-only and a AXI write-only interface into a read-write interface
The read and write interfaces of a AXI bus are independent other than that
they use the same clock. Yet when connecting a single read-only and a
single write-only interface to a Xilinx AXI interconnect it instantiates
arbitration logic between the two interfaces. This is dead logic and
unnecessarily utilizes the FPGAs resources.

Introduce a new helper module that takes a read-only and a write-only AXI
interface and combines them into a single read-write interface. The only
restriction here is that all three interfaces need to use the same clock.

This module is useful for systems which feature a read DMA and a write DMA.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 3e0b337eae axi_ad9963: Remove extra pipeline stages on register read path
The register read logic is not that complicated that it needs two extra
pipeline stages. It can easily be condensed into a single combinatorial and
still meet timing with large margins.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 64dfa0432d axi_ad9963: Disable unused features of the register map
Disable registers in the register map which are not needed for this core.
This reduces the utilization of the core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 957730c421 up_dac_common: Allow to disable GPIO registers
Not all peripherals use the GPIO register settings, but the registers still
take up a fair amount of space in the register map. Add options to allow to
disable them when not needed. This helps to reduce the utilization for
peripherals where these features are not needed.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 0ae0da488b up_adc_common: Allow to disable GPIO and START_CODE registers
Not all peripherals use the GPIO and START_CODE register settings, but the
registers still take up a fair amount of space in the register map. Add
options to allow to disable them when not needed. This helps to reduce the
utilization for peripherals where these features are not needed.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:38 +02:00
Adrian Costina 71394ee465 kcu105: ip automatic version update 2017-04-18 11:59:54 +03:00
Adrian Costina 942d69a30c Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU 2017-04-18 10:57:16 +03:00
Adrian Costina 8e0c87e089 pluto: cleaned up some warnings 2017-04-18 10:34:13 +03:00
Adrian Costina f3c0be0868 motcon2_fmc: cleaned up some warnings 2017-04-18 10:33:13 +03:00
Adrian Costina 6e14cdb5f4 cftl_std: cleaned up some warnings 2017-04-18 10:32:28 +03:00
Adrian Costina d585d65692 cftl_cip: cleaned up some warnings 2017-04-18 10:29:20 +03:00
Adrian Costina 20672a3a8b mitx045: ip automatic version update 2017-04-14 17:46:25 +03:00
Adrian Costina 954037a716 microzed: ip automatic version update 2017-04-14 17:24:24 +03:00
Adrian Costina ebc04bcd9c usdrx1: ip automatic version update 2017-04-14 17:16:35 +03:00
Adrian Costina 24b797f1a6 motcon2: ip automatic version update 2017-04-14 17:11:08 +03:00
Adrian Costina 4981e6e525 usb_fx3: ip automatic version update 2017-04-14 16:55:30 +03:00
Adrian Costina c419b0042b pluto: ip automatic version update 2017-04-14 16:55:07 +03:00
Adrian Costina 79174422b6 imageon: ip automatic version update 2017-04-14 16:54:42 +03:00
Adrian Costina 4bda0c3a1a cftl_cip: ip automatic version update 2017-04-14 16:54:07 +03:00
Adrian Costina afe8b071a3 cftl_std: ip automatic version update 2017-04-14 16:53:10 +03:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
AndreiGrozav 04a4001dba Ip automatic version update: fmcadc2, fmcadc5 2017-04-12 19:03:16 +03:00
AndreiGrozav 627f78ec19 Ip automatic version update: common/board
- vc707
- zc702
- zed
2017-04-12 19:03:16 +03:00
Istvan Csomortani 3f0633aadc spi_engine: Fix CMD_FIFO_VALID generation
Because of the memory map interface mux, up_waddr_s and up_wreq_s should be
used, when cmd_fifo_in_valid is generated.
2017-04-12 14:57:22 +02:00
Rejeesh Kutty 6d2b3bc1c7 adi_project- try something simple first 2017-04-11 14:27:35 -04:00
Rejeesh Kutty 1d9a8a24dc adi_board- create_bd_cell replacement 2017-04-11 14:26:02 -04:00
AndreiGrozav bc9483c5a2 Ip automatic version: Update ad*/common/ad*_bd.tcl
ad6676evb/common/ad6676evb_bd.tcl
ad7616_sdz/common/ad7616_bd.tcl
ad7768evb/common/ad7768evb_bd.tcl
ad9265_fmc/common/ad9265_bd.tcl
ad9434_fmc/common/ad9434_bd.tcl
ad9467_fmc/common/ad9467_bd.tcl
ad9739a_fmc/common/ad9739a_fmc_bd.tcl
adrv9371x/common/adrv9371x_bd.tcl
adv7511/common/adv7511_bd.tcl
fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 18:52:37 +03:00
Rejeesh Kutty 454e6c0382 daq2- ad-ip-instance & ad-ip-parameter 2017-04-06 13:04:53 -04:00
Rejeesh Kutty 2535165461 xilinx- ad-ip-instance & ad-ip-parameter 2017-04-06 13:04:19 -04:00
Rejeesh Kutty 80f93e6a31 zc706- ad-ip-instance & ad-ip-parameter 2017-04-06 13:03:22 -04:00
Rejeesh Kutty 820874ef93 adi_board- add auto ip version handling 2017-04-06 13:02:17 -04:00
Istvan Csomortani c1bdfca4c3 library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00