Commit Graph

75 Commits (c5c772127dd791e07503ea53433b908ac81fb1c4)

Author SHA1 Message Date
Istvan Csomortani aa5fdf903e Makefile: Update makefiles 2019-08-26 16:58:01 +03:00
Arpadi 0680e44330 system_id: deployed ip 2019-08-06 16:53:11 +03:00
Istvan Csomortani a589753d92 project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 43725429ac adi_project: Rename the process adi_project_xilinx to adi_project 2019-06-29 06:53:51 +03:00
Istvan Csomortani 019390f9bf block_design: Updates with new reset net variables 2019-06-11 18:13:06 +03:00
Istvan Csomortani 7960b00684 block_design: Update with new clock net variables
Using the new clock net variables in all Xilinx block designs.
2019-06-11 18:13:06 +03:00
Laszlo Nagy 4ce153e6e1 all/system_top.v: loopback gpio lines
Create loopback on unused GPIO lines since Linux may rely on it.
2018-10-04 14:19:37 +03:00
Laszlo Nagy 31318cf311 all/system_top.v: drive unused gpio inputs with zero
The loopback on the unused gpio inputs consumes routing resources
while does not gives any value for the software.

Connect these lines to zero instead.
2018-08-10 17:00:11 +03:00
AndreiGrozav ebae8bf8c1 Remove interrupts from system_top for all xilinx projects
- remove interrupts from system_top
- for all suported carriers:
	- remove all interrupt bd pins
	- connect to GND all initial unconnected interrupt pins
- update ad_cpu_interrupt procedure to disconnect a interrupt from GND
before connectiong it to another pin.
2018-08-10 10:10:58 +03:00
AndreiGrozav 74288cf9cb axi_hdmi_tx: Added INTERFACE parameter for selecting the interface type
Update all carriers/projects bd for configurable video interface:
- common zc702, zc706, zed
- adrv9361z7035/ccfmc_lvds
- imageon
2018-07-24 15:56:22 +03:00
Adrian Costina 6e7b19c944 Remove projects we don't support anymore 2018-06-15 16:17:48 +03:00
Lars-Peter Clausen b20714bae2 Regenerate project top-level Makefiles
Removes a lot of boilerplate code.

Using the new scheme it is possible to add new projects or sub-projects
without having to re-generate any existing Makefiles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 377247a434 Regenerate project Makefiles using the new shared Makefile includes
This reduces the amount of boilerplate code that is present in these
Makefiles by a lot.

It also makes it possible to update the Makefile rules in future without
having to re-generate all the Makefiles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
Istvan Csomortani a740b6012f Make: Use $(MAKE) for recursive make commands
This commit should resolve the issue #64.

Recursive make commands should always use the variable MAKE, not the explicit
command name ‘make’.
2018-03-07 07:40:19 +00:00
Adrian Costina b7ca17f02b scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Adrian Costina 79174422b6 imageon: ip automatic version update 2017-04-14 16:54:42 +03:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
Lars-Peter Clausen 84a76b9dea imageon: Invert HDMI TX clock
The ADV7511 samples the parallel data bus at the rising edge of sample
clock. Generate the clock so that the falling edge is aligned to updating
the bus data. This creates larger timing margins on each side of the
sampling edge and makes the design more robust.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-29 15:43:24 +01:00
Lars-Peter Clausen 24cc8d284b imageon: Increase RX DMA FIFO size
Increase the RX DMA FIFO to be able to better compensate for momentarily
memory bus contention. This has shown to resolve occasional overflows that
would occur under high system memory load.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-29 14:12:39 +01:00
Lars-Peter Clausen 99dae73d96 imageon: Connect hdmi_rx_core output clock to DMA
Connect the HDMI RX core output clock to the DMA rather than connecting the
HDMI RX input clock directly. This will allow the HDMI RX core to modify
the clock and e.g. insert clock buffers or similar.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-29 14:12:39 +01:00
Lars-Peter Clausen 07217740b5 imageon: Increase HDMI RX clock constraint
The ADV7611 is rated for a maximum clock rate of 165MHz. Increase the clock rate constraint to match this.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-29 14:12:39 +01:00
Adrian Costina b3d3876dc5 imageon: ZC706, updated system_top to remove part of the Warnings.
- constraints fixed so Vivado doesn't issue a Warning
2016-10-10 17:33:42 +03:00
Adrian Costina 9efc45f0b6 imageon: Zed, updated system_top to remove part of the Warnings.
- spi csn signals should be tied to 1 if spi is not used
- constraints fixed so Vivado doesn't issue a Warning
2016-10-10 17:31:25 +03:00
Istvan Csomortani 0cd608a7e2 lib_refactoring: Update Make files 2016-08-08 16:38:38 +03:00
Istvan Csomortani df36902713 lib_refactoring: Fix path of the IO macros 2016-08-08 15:07:19 +03:00
Adrian Costina d60bce654c Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools 2016-08-05 15:16:04 +03:00
Rejeesh Kutty e42b4ea378 hdlmake- updates 2016-08-04 13:28:25 -04:00
Istvan Csomortani 7ca8e10004 make: Update Make files 2016-08-01 14:24:48 +03:00
AndreiGrozav 69a68a99e0 imageon/zed - remove onboard hdmi and update design 2016-07-01 14:11:49 +03:00
Rejeesh Kutty ebdc7832a7 hdl make updates 2016-06-01 14:00:30 -04:00
Rejeesh Kutty bfeebc2791 imageon/zc706- remove onboard hdmi 2016-06-01 13:59:13 -04:00
Rejeesh Kutty eca4d4e2a6 imageon/zc706- board updates 2016-06-01 13:59:13 -04:00
AndreiGrozav 21208ca208 Makefiles: Update Makefiles 2016-03-31 12:37:47 +03:00
AndreiGrozav d567af54ef imageon: Update common design to 2015.4 2016-03-18 15:27:31 +02:00
Adrian Costina 9d2b8809df Makefiles: Updated Makefiles 2015-10-23 10:44:27 +03:00
Rejeesh Kutty ed918ec119 imageon - keeping scripts happy 2015-10-16 15:04:02 -04:00
Istvan Csomortani 4aa4ffc25f imageon/common: Update cores to Vivado 2015.2 2015-09-29 18:51:46 +03:00
Istvan Csomortani e60d2f86b3 imageon/common: Fix parameter name for spdif_rx 2015-09-29 18:50:41 +03:00
Lars-Peter Clausen 8d179235f8 imageon: Drop explicit axi_dmac clock synchronicity configuration
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:14 +02:00
Istvan Csomortani d52308f074 axi_dmac: Change parameter name 2D_TRANSFER
Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 10:14:22 +03:00
Istvan Csomortani 57cfb7cfb1 hdl/library: Update the IP parameters
The following IP parameters were renamed:

PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
Adrian Costina a7da779b94 Makefile: Updated Makefiles 2015-07-16 18:19:42 +03:00
Adrian Costina 897c31ebbf imageon: moved spdif_rx to DMA3 to be compatible with both zc706 and zed 2015-07-09 10:58:54 +03:00
Istvan Csomortani 46fa91d5be Makefile: Update Make files 2015-07-03 18:08:57 +03:00
Istvan Csomortani 8c98399c37 imageon_ZC706: Add axi_spdif_rx core to the design 2015-07-03 17:48:29 +03:00
Lars-Peter Clausen eb3a0c179b imageon: Put HDMI input/output FF into the IOB
This gives us predictable delays as well as very small skew between the induvidual data lines.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-02 18:33:32 +02:00