Istvan Csomortani
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c46989e4e8
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Makefile: Update Makefiles for libraries
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2017-03-30 18:33:22 +03:00 |
Istvan Csomortani
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31a5c674f2
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fmcomms2: Update constraints file paths
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2017-03-30 16:16:02 +03:00 |
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Istvan Csomortani
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ea7e93d27f
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fmcomms2: Use the new constriants from 335fef0
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2017-03-29 18:36:09 +03:00 |
Rejeesh Kutty
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1ef064ac03
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axi_ad9361- add receive init delay
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2017-03-13 16:28:38 -04:00 |
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Rejeesh Kutty
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0ae79ca7ac
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move/rename - delay script belongs to ad9361
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2017-03-10 12:44:32 -05:00 |
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Istvan Csomortani
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6b90054343
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axi_ad9361: Define CDC constraint for tdd_sync
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2017-02-24 11:24:07 +02:00 |
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Istvan Csomortani
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94bda1d415
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axi_ad9361: Preserve 1bit CDCs with ASYNC_REG true
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2017-02-23 11:43:10 +02:00 |
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Istvan Csomortani
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2b354af876
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axi_ad9361_tdd: Register the tdd_sync_cntr output
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2017-02-23 11:31:23 +02:00 |
Adrian Costina
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8ebc8fe4e2
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updated makefiles
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2016-12-09 23:06:41 +02:00 |
AndreiGrozav
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9d6c93a5d8
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Fix warnings
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2016-11-14 15:17:15 +02:00 |
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Rejeesh Kutty
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1e0fed82f7
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alt_serdes- a10 ddio fixes
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2016-11-01 12:41:25 -04:00 |
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Rejeesh Kutty
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9f4c5f8060
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arradio/ad9361- updates
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2016-10-31 15:34:32 -04:00 |
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Rejeesh Kutty
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b94cc8afb1
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altera- cmos cores
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2016-10-31 13:13:48 -04:00 |
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Rejeesh Kutty
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cc75fa3dfe
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altera- java/tcl mess handling
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2016-10-31 10:54:07 -04:00 |
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Rejeesh Kutty
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a9d03af771
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altera- serdes changes
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2016-10-28 14:09:18 -04:00 |
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AndreiGrozav
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08cef5a745
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axi_ad9361: Add Cyclone V SERDES support
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2016-10-25 20:24:17 +03:00 |
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AndreiGrozav
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1131be91ed
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axi_ad9361: Makefile update
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2016-10-11 23:34:13 +03:00 |
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AndreiGrozav
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b7767aa18f
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xilinx/axi_ad9361_lvds_if: Remove ila
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2016-10-11 18:13:45 +03:00 |
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AndreiGrozav
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369dad60b0
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axi_ad9361: Add Altera SERDES interface support
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2016-10-11 17:59:19 +03:00 |
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AndreiGrozav
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52194f0fea
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axi_ad9361: Add DRP connection to the interface module
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2016-10-11 17:59:12 +03:00 |
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AndreiGrozav
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7194d2eccc
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axi_ad9361: Grup interfaces to add support for more carriers
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2016-10-11 17:58:49 +03:00 |
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Istvan Csomortani
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1b9d2d434c
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axi_ad9361_tdd: Delete unused register
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2016-10-05 17:41:08 +03:00 |
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Istvan Csomortani
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43b3761b80
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axi_ad9361: Flop the tx and rx valid
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2016-10-03 12:24:04 +03:00 |
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Rejeesh Kutty
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b4fac96aad
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axi_ad9361- independent disables
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2016-09-28 15:45:27 -04:00 |
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Istvan Csomortani
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f7fb3ccaca
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axi_ad9361: Change the data path gating
Bring up the datapath gating from the TDD controller module.
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2016-09-28 16:36:13 +03:00 |
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Rejeesh Kutty
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1a11e28821
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ad9361- dac data path split
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2016-09-23 16:13:46 -04:00 |
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Rejeesh Kutty
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7be6168b2e
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ad9361- adc data path split
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2016-09-23 13:42:14 -04:00 |
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Rejeesh Kutty
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78f7384150
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ad9361- vivado synthesis warnings fix
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2016-09-22 13:41:18 -04:00 |
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Istvan Csomortani
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913eafed48
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up_drp : Update the DRP interface to support Altera platforms
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2016-09-21 15:00:45 +03:00 |
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Istvan Csomortani
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2159f78c80
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axi_ad9361: Delete invalid assignment of a generated wire
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2016-09-16 17:38:08 +03:00 |
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Istvan Csomortani
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a183e51a12
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axi_ad9361: Add parameter R1_MODE_EN
R1_MODE_EN can disable the second I/Q channel of the core. This way
the user can save resources by cutting down the size of the core.
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2016-09-09 16:34:11 +03:00 |
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Istvan Csomortani
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e42206e510
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axi_ad9361: Add a TDD enable/disable parameter
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2016-09-09 14:38:28 +03:00 |
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Istvan Csomortani
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be41a8bcaa
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axi_ad9361: Delete debug ports of the tdd module
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2016-09-09 14:38:28 +03:00 |
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Rejeesh Kutty
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9799599eee
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library/ad9361- add dac clk sel
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2016-08-26 10:31:00 -04:00 |
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Adrian Costina
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6a8ca8107a
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common: Added common ad_dcfilter stub for altera.
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2016-08-16 17:37:16 +03:00 |
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Istvan Csomortani
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0cd608a7e2
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lib_refactoring: Update Make files
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2016-08-08 16:38:38 +03:00 |
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Istvan Csomortani
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aad8c265bc
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lib_refactoring: Fix path for CMOS sources
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2016-08-08 15:07:54 +03:00 |
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Istvan Csomortani
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df36902713
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lib_refactoring: Fix path of the IO macros
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2016-08-08 15:07:19 +03:00 |
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Adrian Costina
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d60bce654c
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Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
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2016-08-05 15:16:04 +03:00 |
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Istvan Csomortani
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58b220ba81
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ad_tdd_control: Add an on/off switch to the receive datapath
For a more robust control, add an on/off switch to the receive datapath too,
in order to filter out transition noises.
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2016-08-01 11:49:27 +03:00 |
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Rejeesh Kutty
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7485d27d37
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ad9361/altera- device-family variable
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2016-06-14 12:28:13 -04:00 |
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Rejeesh Kutty
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5d437083cc
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ad9361/altera- a10+ only
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2016-06-14 12:19:54 -04:00 |
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Rejeesh Kutty
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c293c04634
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hdl make updates
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2016-06-01 13:53:09 -04:00 |
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Rejeesh Kutty
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a262eb7ab3
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ad9361- output-rst - associated-rst issue?
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2016-05-18 13:24:13 -04:00 |
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Rejeesh Kutty
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d7f0bd1b76
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ad9361- add reset sink
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2016-05-18 13:24:13 -04:00 |
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Rejeesh Kutty
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bb4ed42a93
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ad9361- add missing wires
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2016-05-18 13:24:13 -04:00 |
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Rejeesh Kutty
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68329de738
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ad9361- interface updates
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2016-05-16 12:19:38 -04:00 |
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Rejeesh Kutty
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3871d3ce2b
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ad9361-c5/a10 - updates
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2016-05-09 13:54:08 -04:00 |
|
Rejeesh Kutty
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bdfa383622
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library/axi_ad9361: tdd false paths
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2016-05-04 13:42:12 -04:00 |
|
Rejeesh Kutty
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ef6c99ecab
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library/axi_ad9361: hw component updates
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2016-05-04 13:42:12 -04:00 |