Commit Graph

231 Commits (c637d848bbdc56bf07dbdf0fe37b7734a4a1773e)

Author SHA1 Message Date
Istvan Csomortani ebfed4b24b ad_axi_ip_constr.xdc: Delete file 2017-03-30 16:16:02 +03:00
Istvan Csomortani 8ba6012b6b restructure: Move xilinx specific constraints to /library/xilinx/common/ 2017-03-30 16:16:02 +03:00
Istvan Csomortani 335fef0f42 ad_axi_ip_constr: Split up this constraint file into separate files
For experimentation, to solve a constraint scoping issue, split up the
ad_axi_ip_constraint file into separate constraints file, in function
of there parent module.
2017-03-29 18:31:40 +03:00
Rejeesh Kutty b0e88eb5ff axi_ad9361- add receive init delay 2017-03-13 16:28:24 -04:00
Istvan Csomortani 1d6ddacfd6 axi_ip_constr: Fix constraints
The filter for CDC registers were too generic, and a few non-CDC
register were set as asynchronous register.
2017-02-27 16:25:09 +02:00
Istvan Csomortani 2da7dd4079 axi_ip_constr: Update constraints
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-23 11:33:25 +02:00
Rejeesh Kutty db924953bb altera- warnings about init values 2017-01-30 10:01:28 -05:00
Adrian Costina 3f3a8bd267 library: forced ad_mem module to be implemented in BRAM for Xilinx devices 2017-01-25 18:12:04 +02:00
Rejeesh Kutty c0a2ef1ac4 library- altera power up warnings 2016-12-20 16:18:15 -05:00
Istvan Csomortani ce47cf8d30 ad_sysref_gen: Fix sysref generation
Toggle sysref output just if the sysref_en is asserted.
2016-12-19 18:02:49 +02:00
Istvan Csomortani a228c05bd3 common: Add a SYSREF generation module
The SYSREF generator is using a simple free running counter,
which runs on the JESD204 core clock. The period can be
configured using a parameter, it must respect the constraints
defined by the JESD204 standard.
The generator can be enabled through a GPIO line.
2016-12-17 11:12:10 +02:00
Istvan Csomortani a00d9870be axi_ip_constr: Fix constraints
Modify a contraint for a false path, so it will be applied to
up_delay_cntr module too.
2016-12-16 12:01:38 +00:00
Istvan Csomortani 12d6e46ae7 clean: Delete deprecated source files
The axi_jesd_gt was repleaced by axi_adxcvr IP, which is located
at library/xilinx and library/altera.
The axi_jesd_xcvr was an early version of axi_adxcvr.
The register map is moved to the IP's directory.
2016-11-14 10:43:46 +02:00
Istvan Csomortani 5eff357568 up_tdd_cntrl: Fix memory map register writes 2016-11-01 10:06:57 +02:00
Istvan Csomortani 8e25bc01b3 all: Change tab to double space
Occasional file parsing and restructuring become a pain, if tabs exists
in code. General rule of the repos is tab always a double space.
2016-10-01 18:13:42 +03:00
Rejeesh Kutty 6735333aea common- dac data path split 2016-09-23 16:13:24 -04:00
Rejeesh Kutty 8729af1b91 common- adc- data path disable split 2016-09-23 13:40:35 -04:00
Rejeesh Kutty 78f7384150 ad9361- vivado synthesis warnings fix 2016-09-22 13:41:18 -04:00
Istvan Csomortani 2b6eb1d65e up_drp: Revert some bit locations
Linuxe drivers are checking the drp_locked status even if the
core does not contains a clock generation/managment module. To
not break all the designs, revert all the status and control bits to
there old locations.
2016-09-22 16:32:42 +03:00
Istvan Csomortani a21b9fe8ff up_drp: Fix up_drp_wr 2016-09-21 17:55:58 +03:00
Istvan Csomortani 913eafed48 up_drp : Update the DRP interface to support Altera platforms 2016-09-21 15:00:45 +03:00
Dragos Bogdan 10408b8c88 up_tdd_cntrl: Set PCORE version to 1.00.a 2016-09-21 10:27:28 +03:00
Rejeesh Kutty 74bc498a6d library/common- added dac clock select 2016-08-26 10:31:00 -04:00
Rejeesh Kutty e754f0a46a up_axi- writes dropped by delayed w-responses 2016-08-14 11:21:19 -04:00
Istvan Csomortani 1d33d7d7ee lib_refactoring: Move the CMOS interface modules to ~/library/xilinx/common 2016-08-08 15:07:42 +03:00
Istvan Csomortani 90ac7b7ac9 lib_refactoring: Move all Altera module to library/altera/common
Move all Altera modules to library/altera/common, delete the
deprecated wrapper files
2016-08-08 15:07:01 +03:00
Istvan Csomortani b806fa3b42 lib_refactoring: Move all the Xilinx common modules to library/xilinx/common 2016-08-08 15:06:10 +03:00
Matthew Fornero b99117e686 up_axi: Same cycle BVALID/READY fails on Altera
The Qsys interconnect does not handle the assertion of BVALID on the
same cycle as [A]WREADY. Add a single cycle of delay to prevent
deadlocks.

Similar to:
2817ccdb22
("up_axi: altera can not handle same clock assertion of arready and rvalid")

Signed-off-by: Matthew Fornero <matt.fornero@mathworks.com>
2016-08-01 12:17:10 +03:00
Istvan Csomortani 58b220ba81 ad_tdd_control: Add an on/off switch to the receive datapath
For a more robust control, add an on/off switch to the receive datapath too,
in order to filter out transition noises.
2016-08-01 11:49:27 +03:00
Shrutika Redkar 8a2734b43e up_dac_common- typo- unf register reset 2016-07-28 13:44:57 -04:00
Rejeesh Kutty db6d5f509f library/common- xcvr interface logic 2016-07-21 16:09:33 -04:00
Rejeesh Kutty ced36f6159 up-dac- support iq mode 2016-07-21 11:58:03 -04:00
Istvan Csomortani 040f72d172 ad_mul_u16: Delete unused module 2016-07-20 14:17:04 +03:00
Istvan Csomortani 2dd6bb0cb8 up_drp_cntrl: Delete unused module 2016-07-20 14:17:04 +03:00
Istvan Csomortani af9915b060 up_axis_dma_*: Delete unused modules 2016-07-20 14:17:04 +03:00
Istvan Csomortani df43ca9332 ad_axis_dma_*: Delete unused modules 2016-07-20 14:17:04 +03:00
Istvan Csomortani 64633e519c Merge remote-tracking branch 'origin/dev_ad7616' into dev 2016-06-29 12:32:39 +03:00
AndreiGrozav aee38e1cc9 up_hdmi_tx: Fixed data path width 2016-06-14 14:27:03 +03:00
Istvan Csomortani 9d1ae436b1 common/util_pulse_gen: Rename the ad_tdd_sync module 2016-06-09 10:07:47 +03:00
AndreiGrozav f10c1e6e93 axi_hdmi_tx: Remove hdmi_full_range register 2016-05-27 14:04:40 +03:00
Rejeesh Kutty 6bc05fc844 ad_*_in: register post-iob 2016-05-16 12:19:38 -04:00
Rejeesh Kutty cd7c9c99ed ad_*_clk: altera-pll not supported by qsys flow 2016-05-16 12:19:38 -04:00
Rejeesh Kutty 9cd6e2da51 quartus-mess- altddio direct instantiation 2016-05-09 13:54:08 -04:00
AndreiGrozav 726ddb6e93 ad_lvds_clk: Fixed assignment mismatched 2016-05-09 10:32:18 +03:00
AndreiGrozav b36c722ec9 up_hdmi_tx: Discard the standard default values
Restore the base functionality of the core. Changing the data format
will not set by default its standard maximum and minimum data clipping
ranges.
2016-05-05 13:41:46 +03:00
Rejeesh Kutty d82ca5dc3c library/common- altera variations 2016-05-04 13:42:11 -04:00
Rejeesh Kutty 89f5d2394e altera- clock variations 2016-04-29 10:17:35 -04:00
Rejeesh Kutty 3563c2212c common/altera- removed dcfilt/mul 2016-04-29 10:17:35 -04:00
Rejeesh Kutty 0260280db1 common/altera- data path 2016-04-29 10:17:35 -04:00
Rejeesh Kutty ed62101308 common/altera: primitives 2016-04-29 10:17:35 -04:00