Commit Graph

4979 Commits (c7098a9d49568661def90ba8f890fa263e6ad46f)

Author SHA1 Message Date
Sergiu Arpadi c7098a9d49 axi_fan_control: Initial commit 2019-04-15 13:06:37 +03:00
Istvan Csomortani 42d2738a30 axi/util_adxcvr: Add GTYE4 transceiver support 2019-04-12 16:19:54 +03:00
AndreiGrozav 7ce39c4000 adrv9361z7035_ccbob_cmos: Use ad_rst constraints file
The file was excluded by mistake.
2019-04-12 10:48:50 +03:00
Laszlo Nagy 4b13274c55 ad9361/all/system_constr.xdc: remove manual clock definition
Having a clock assigned manually to the clk output pin of the axi_ad9361
let the Vivado timing engine to not ignore the clock insertion delay when
analyzing paths between clk_0 and the manually created clock that has
the same source (clk_0), resulting in timing failure.
2019-04-12 10:48:50 +03:00
AndreiGrozav bd79a0040e common/vc707: Tools version update (2018.3)
Use 200MHz clock for Ethernet subsystem ref_clk
2019-04-12 10:48:50 +03:00
AndreiGrozav e1f0b301d3 Tools version upgrade
Vivado 2018.2 -> Vivado 2018.3
Quartus 18.0  -> Quartus 18.1
2019-04-12 10:48:50 +03:00
AndreiGrozav 23841478c6 Remove library/scripts/common_bd.tcl
Remove the script from the file list of the IPs that previously used it.
axi_clkgen: Add independent adi_auto_assign_device_spec proc
2019-04-09 16:07:14 +03:00
AndreiGrozav 7dcaaea04e library: Update scripts/adi_ad_ip.tcl and IPs
Fix library makefiles dep list using generic vendor info reg

Combine adi_int_bd_tcl with adi_auto_fill_bd_tcl procedure.
This change will simplify the process of generating makefiles for each library.
Removing the bd.tcl script from the adi_ip_files list will remove it from the
make dependency list.
2019-04-09 16:07:14 +03:00
Edward Kigwana 036dc92b55 up_axi: Remove dead code.
Signed-off-by: Edward Kigwana <ekigwana@scires.com>
2019-04-09 14:27:31 +03:00
István Csomortáni 46d1ae58e9
README: Fix a typo 2019-04-03 10:21:36 +03:00
AndreiGrozav 4ae5a6d3d8 library/IPs: Auto-generate bd.tcl Update
Remove all bd.tcl and respecting the previous commit, update *_ip.tcl to
auto-generate bd.tcl for:

  - axi_ad5766/axi_ad5766_ip.tcl
  - axi_ad6676/axi_ad6676_ip.tcl
  - axi_ad9122/axi_ad9122_ip.tcl
  - axi_ad9144/axi_ad9144_ip.tcl
  - axi_ad9152/axi_ad9152_ip.tcl
  - axi_ad9162/axi_ad9162_ip.tcl
  - axi_ad9250/axi_ad9250_ip.tcl
  - axi_ad9265/axi_ad9265_ip.tcl
  - axi_ad9361/axi_ad9361_ip.tcl
  - axi_ad9371/axi_ad9371_ip.tcl
  - axi_ad9434/axi_ad9434_ip.tcl
  - axi_ad9467/axi_ad9467_ip.tcl
  - axi_ad9625/axi_ad9625_ip.tcl
  - axi_ad9671/axi_ad9671_ip.tcl
  - axi_ad9680/axi_ad9680_ip.tcl
  - axi_ad9684/axi_ad9684_ip.tcl
  - axi_ad9739a/axi_ad9739a_ip.tcl
  - axi_ad9963/axi_ad9963_ip.tcl
  - axi_adrv9009/axi_adrv9009_ip.tcl
  - axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl
  - axi_hdmi_tx/axi_hdmi_tx_ip.tcl
  - xilinx/axi_adxcvr/Makefile
  - xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
  - xilinx/util_adxcvr/Makefile
  - xilinx/util_adxcvr/util_adxcvr_ip.tcl
2019-03-30 11:26:11 +02:00
AndreiGrozav 99412a503e library/scripts/*xilinx*: Auto-generate bd.tcl
Having a bd.tcl script in every IP is redundant.

adi_ip.tcl:
 - add adi_init_bd_tcl - creates a blanch bd.tcl and a
parameters temporary_case_dependencies.mk when compiling an IP.
Its main purpose is to generate the bd.tcl, which will be included in
the IP's file-set.
 - adi_auto_fill_bd_tcl will populate the empty bd.tcl based on the
top IP parameters and the presence of these parameters in
auto_set_param_list and auto_set_param_list_overwritable lists.
This task can not be performed by the first described procedure since
the file-set is not yet defined.

adi_xilinx_device_info_enc.tcl:
Split auto_set_param_list_overwritable from auto_set_param_list. As
the name states, some of the parameters are overwritable, this will help
when generating the bd.tcl script.

library.mk:
Include the temporary_case_dependencies.mk if it exists in the
IP root folder. The mentioned *.mk file contains non generic
dependencies for makefiles like targets to clean.
2019-03-30 11:26:11 +02:00
AndreiGrozav f4dda7f2d3 Remove unused script 2019-03-30 11:26:11 +02:00
AndreiGrozav f29e91a440 adi_intel_device_info_enc.tcl: Add all known intel supported packages 2019-03-30 11:26:11 +02:00
AndreiGrozav 7dcb2050c7 dev info parameter update: Increase pcore version 2019-03-30 11:26:11 +02:00
AndreiGrozav ceb08feee2 Add license header on tcl files 2019-03-30 11:26:11 +02:00
AndreiGrozav d894c30c2d Remove deprecated/unused parameters
adrv9009
adrv9371x
arradio
daq2
daq3
fmcomms2
fmcomms5
2019-03-30 11:26:11 +02:00
AndreiGrozav 66823682b6 Add FPGA info parameters flow
Common basic steps:
- Include/create infrastructure:

   * Intel:
       - require quartus::device package
       - set_module_property VALIDATION_CALLBACK info_param_validate

   * Xilinx
       - add bd.tcl, containing init{} procedure. The init procedure will be
         called when the IP will be instantiated into the block design.
       - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl
       - create GUI files

- add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params)
- add/propagate the info parameters through the IP verilog files

axi_clkgen
util_adxcvr
ad_ip_jesd204_tpl_adc
ad_ip_jesd204_tpl_dac
axi_ad5766
axi_ad6676
axi_ad9122
axi_ad9144
axi_ad9152
axi_ad9162
axi_ad9250
axi_ad9265
axi_ad9680
axi_ad9361
axi_ad9371
axi_adrv9009
axi_ad9739a
axi_ad9434
axi_ad9467
axi_ad9684
axi_ad9963
axi_ad9625
axi_ad9671
axi_hdmi_tx
axi_fmcadc5_sync
2019-03-30 11:26:11 +02:00
AndreiGrozav dffbbfd7d1 library/scripts: Add auto dev spec parameters
Xilinx:
When calling adi_auto_fpga_spec_params in the x_ip.tcl, parameters like
- FPGA_TECHNOLOGY
- FPGA_FAMILY
- SPEED_GRADE
- DEV_PACKAGE
- XCVR_TYPE
- FPGA_VOLTAGE
will be automatically detected and constrained to predefined pairs of values
from adi_xilinx_device_info_env.tcl

The parameters specified in the blobk diagram of the IP(bd.tcl), will be
automatically assign when the IP is added to a block design.

The "adi_auto_assign_device_spec $cellpath" is called in the init
hook (bd.tcl).
https://www.xilinx.com/products/technology/high-speed-serial.html

Intel:
Info parameters are set in the VALIDATION_CALLBACK according to
adi_intel_device_info_env.tcl
2019-03-30 11:26:11 +02:00
Adrian Costina 8340d4c89d axi_jesd204_common: Fix dependancies so that the IP can be generated Out Of Context 2019-03-21 15:36:57 +02:00
Istvan Csomortani 04af519af8 axi_adxcvr: Re-indent ports 2019-03-21 14:30:39 +02:00
Istvan Csomortani 845c369c6b axi_adcvr: Add initial value for reg port definition 2019-03-21 14:30:39 +02:00
Istvan Csomortani 8996044978 axi_adxcvr: Fix warning related to up_es_reset
Fix the following warning:

WARNING: [Synth 8-2611] redeclaration of ANSI port up_es_reset is not allowed

Also make sure, that in all configurations, the register has a diver.
2019-03-21 14:30:39 +02:00
Istvan Csomortani 59713f96ab util_tdd_sync: Fix util_pulse_gen instantiation 2019-03-21 07:28:18 +00:00
Istvan Csomortani a337774dfa ad_ip_jesd204_tpl_dac: Add 8 bit resolution support 2019-03-20 15:51:28 +02:00
Istvan Csomortani e3e96177c4 ad_ip_jesd204_tpl_adc: Add 8 bit resolution support
Add support for 8 bit resolution for the transport layer.

Fix parameter BITS_PER_SAMPLES propagation to all the internal modules, in
several cases this variable was hard coded to 16.
2019-03-20 15:51:28 +02:00
Istvan Csomortani ac4d78b95d ad_datafmt: Add support for 8 bit data width 2019-03-20 15:51:28 +02:00
sarpadi 2f68c546f1
Merge pull request #244 from analogdevicesinc/axi_i2s_adi_update
axi_i2s_adi: fixed xdc
2019-03-20 13:42:23 +02:00
sarpadi 470f8cd33b
Merge pull request #245 from analogdevicesinc/dev_axi_pulse_gen
AXI_PULSE_GEN
2019-03-20 10:27:26 +02:00
Istvan Csomortani 0e7b38ebcf axi_pulse_gen: Initial commit
The axi_pulse_gen is a generic PWM generator, which can be configured
through an AXI Memory Mapped interface.

The current register map look like follows:

  0x00 - VERSION
  0x04 - ID
  0x08 - SCRATCH
  0x0C - IDENTIFICATION - 0x504c5347 which stands for 'PLSG' in ASCII
  0x10 - CONFIGURATION - contains reset and load bits
  0x14 - PULSE_PERIOD
  0x18 - PULSE_WIDTH

Also update all the other modules, which instantiate the util_pulse_gen.
2019-03-20 08:21:22 +00:00
Istvan Csomortani f15ed8475e util_pulse_gen: Change the counter to a down-counter
To prevent the case, when after an invalid configuration, the generated
output PWM signal is constant HIGH, change the counter to a
down-counter. In this way the pulse will be placed at the end of the
PWM period, and if the configured width value is higher than the
configured period the output signal will be constant LOW.
2019-03-20 08:21:08 +00:00
Istvan Csomortani 2d7b189ba3 util_pulse_gen: Add an input configuration port for pulse width attribute 2019-03-19 16:33:10 +00:00
Sergiu.Arpadi 0e333bf5ae axi_i2s_adi: fixed xdc
ip now sets the xdc to late so that the timing constraints are set in the correct context
2019-03-18 13:58:28 +00:00
Laszlo Nagy 8885caab13 scripts/adi_board.tcl: fix HP address mappings for ZynqMP
In the current form, when connecting a master to the HP ports all
available slave address spaces are mapped to the master (DDR_*, PCIE*, OCM,
QSPI)

Let the PL masters have access only to the DDR_LOW and DDR_HIGH address
spaces to avoid unnecessary resource usage and increase timing margin.
2019-02-27 15:04:41 +02:00
Laszlo Nagy a3ce8c5ca6 axi_rd_wr_combiner: Add rlast to the AXI MM interface
The DMAC is relying on the rlast signal that marks the end of a burst.
2019-02-21 17:09:53 +02:00
Laszlo Nagy c10c4d4f5e up_dac_common: fix address decoding
Patch the typo introduced in a previous commit while attempting the
address space reduction.
2019-02-19 15:38:45 +02:00
AndreiGrozav 1c8172de7f axi_adc_trigger: Cosmetic update
Use localparam DW = 15 - SIGN_BITS
2019-02-18 13:39:24 +02:00
AndreiGrozav 44e20d095c axi_adc_trigger: Fix triggering jitter effect 2019-02-18 13:39:24 +02:00
Adrian Costina 6e9bc398c3 fmcomms5: Connect overflow pin between adc_pack and adc_fifo 2019-02-14 14:36:45 +00:00
AndreiGrozav 2ec578c216 axi_hdmi_tx: Update file sources for Intel designs 2019-02-12 10:43:46 +02:00
AndreiGrozav ce04f46b80 motcon2_zed: Fix timing problems
-change implementation strategy
-axi_dmac add extra registers AXI_SLICE_SRC

This was done to increase the overall timing margin.
2019-02-12 10:43:46 +02:00
AndreiGrozav 2d825d8b7c daq3_zc706: Change implementation strategy 2019-02-12 10:43:46 +02:00
AndreiGrozav fae4d478d4 ad_csc: Generalize for CrYCB 2 RGB conversion 2019-02-12 10:43:46 +02:00
AndreiGrozav 74eacc2369 ad_csc(RGB2CrYCb): use signed multiplication. 2019-02-12 10:43:46 +02:00
AndreiGrozav 265781f29a axi_hdmi: Let the tools assign the csc resources
Write code to pipeline data path for better DSP utilization on the
color space conversion.
In the old method the addition operations were performed outside the
DSPs
2019-02-12 10:43:46 +02:00
Adrian Costina 47f7894881 util_adxcvr: Initial commit for QPLL1 support (GTH3 and GTH4) 2019-02-11 17:20:08 +02:00
Laszlo Nagy ca1ba6a6fe axi_ad9144/axi_ad9152: patch up_tpl_common dependency 2019-02-01 08:28:28 +00:00
Istvan Csomortani b2d86bab47 util_axis_fifo: Fix the FIFO level generation in ASYNC mode
The FIFO functions in 'first fall through' mode, adjust the fifo level
generation so it take into account the valid data which sits on the bus,
waiting for ready, too.
2019-01-29 11:38:28 +02:00
Laszlo Nagy b221718bfe jesd204:up_tpl_common: reduce and move address space
Limit the tpl register space to 128 locations mapped to 128-255 in the COMMON_ID segment.
2019-01-23 17:44:33 +02:00
Laszlo Nagy 93df754800 up_adc_common/up_dac_common: reduce address space to half
Limit the adc/dac common space to 128 registers mapped 0-127 in the COMMON_ID segment.
2019-01-23 17:44:33 +02:00