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25 Commits (c7351f3ce32b2c9c3a8aa89220bcda3c53930dda)

Author SHA1 Message Date
Istvan Csomortani e30a80fda0 daq1_spi: Delete device specific macro instantiation 2016-12-06 15:24:21 +02:00
Istvan Csomortani 7e57a89ce5 daq1: Add support for A10GX 2016-10-24 11:43:33 +03:00
Istvan Csomortani 7be017baa3 daq1: Add AXI PLDDR FIFO to the receive path 
The AD9684 has two 500 MSPS converter, the system can not handle this
throughput without a FIFO.
 2016-07-07 07:15:54 +03:00
Istvan Csomortani 9169e20b5e daq1: Fix the data width on the DMAC interfaces 
+ HP ports maximum width is 64 bits
+ DMAC's default width is 64, no need for redefinition
 2016-07-07 07:15:54 +03:00
Rejeesh Kutty 697469ee28 daq1- updates 2016-03-15 12:39:38 -04:00
Adrian Costina 977d9d0624 Merge branch 'hdl_2015_r2' into dev 
Conflicts:
	projects/daq1/common/daq1_spi.v
 2016-03-02 13:52:15 +02:00
Adrian Costina 40fb68dfd5 ad9265, ad9434, ad9467, daq1, daq2, daq3, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1, fmcomms6, fmcomms7, usdrx1: updated common spi module so that spi streaming is possible 2016-03-02 13:39:37 +02:00
Istvan Csomortani 59313f3c90 daq1: ADC DMA must be in none-cyclic mode 2016-02-24 14:37:19 +02:00
Istvan Csomortani c0a559a9b1 daq1: Fix some typos in the SPI wrapper 2016-02-24 14:31:56 +02:00
Istvan Csomortani c32d7147d5 daq1 : There is a single CSN from master 2016-02-12 14:38:32 +02:00
Istvan Csomortani 8c69c9d2ce daq1_zc706 : Update the project 
+ Add AD9684 to the block design
+ Update the IO definitions
+ Update the CPLD design
+ Add 3wire SPI logic
 2016-01-19 11:20:35 +02:00
Istvan Csomortani d52308f074 axi_dmac: Change parameter name 2D_TRANSFER 
Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
 2015-08-20 10:14:22 +03:00
Istvan Csomortani 57cfb7cfb1 hdl/library: Update the IP parameters 
The following IP parameters were renamed:

PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
 2015-08-19 14:11:47 +03:00
Istvan Csomortani 2330d1e27d daq1/common: The new GT module does not have integrated monitor/debug ports 2015-06-09 11:50:27 +03:00
Rejeesh Kutty 71b5004b25 projects- drp moved to up-clock domain 2015-06-01 14:57:59 -04:00
Adrian Costina 3b58785368 daq1: Updated jesd reset connection. Fixed dmac async configuration. Updated zc706 constraints 2015-04-30 12:14:03 +03:00
Istvan Csomortani 75d2c7e93e daq1_zc706: Update project to the new framework 2015-03-24 12:45:24 +02:00
Istvan Csomortani 68ac015825 daq1_fmcl: Fix GT lane number definitions 
Update which fix issues caused by GT lane number parameters change. (commit f8e7796592)
 2014-11-24 18:23:33 +02:00
Istvan Csomortani 0ecfc14e95 daq1_fmc: Update interrupts. 2014-11-24 18:23:32 +02:00
Istvan Csomortani 9b104f1657 daq1_fmc: Get rid of the concat module inside the block design. 
xl_concat just causing troubles, no need to use it, if not justified.
 2014-11-24 18:23:30 +02:00
Istvan Csomortani 17675863e0 all_projects: Fix the interrupt connections to preserve IRQ layout 2014-10-22 11:48:08 +03:00
Rejeesh Kutty 577441bd0c daq1: clean up dma interfaces 2014-09-23 14:23:41 -04:00
Istvan Csomortani dd7bac41c1 daq1 : Update project to 2014.2 
- Cores are upadted
  - Concat module does not swap output anymore
  - Clock signal name ps7_clk_* changed to clk_fpga_*
 2014-09-22 17:33:50 +03:00
Istvan Csomortani a91f4bb6b9 daq1: General updates 
- Add additional GT setups
- Use channel PLL instead of quad PLL
- Add additional ILA probes for debug
 2014-09-13 00:23:11 +03:00
Istvan Csomortani ee752ec08a daq1: Initial commit 2014-09-01 18:34:31 +03:00