Rejeesh Kutty
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9b6dd27c23
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ad9361- delay initialization
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2017-03-15 12:06:59 -04:00 |
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Rejeesh Kutty
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1b3f752c3d
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pzsdr1/pzsdr2/pluto- add iodelay report
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2017-03-10 12:55:22 -05:00 |
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Rejeesh Kutty
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c598e84258
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remove processing order (no clock def dependency)
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2017-02-22 16:02:08 -05:00 |
Adrian Costina
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46290193f3
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pzsdr2: ccusb, renamed clk_out to clkout_in
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2017-02-14 11:58:11 +02:00 |
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Adrian Costina
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319a883c00
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pzsdr2: Added FIFOs for DAC and ADC paths so that they work at l_clk/2 or l_clk/4
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2017-01-18 12:00:10 +02:00 |
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Adrian Costina
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6e89ac3d65
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pzsdr2: ccusb_lvds, add flag_a,flag_b signals
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2016-11-30 17:39:02 +02:00 |
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Adrian Costina
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3d0049d274
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pzsdr2: ccusb_lvdsr, updated project for the latest schematic
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2016-11-22 16:55:52 +02:00 |
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Rejeesh Kutty
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cfd3ea61f1
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pzsdr-to-pzsdr2
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2016-11-14 14:12:22 -05:00 |