680d28476c
ad9081_fmca_ebz: Add LANE_RATE param to all projects
...
The block design expects a lane rate to be set in the system project.
2021-05-14 15:39:40 +03:00
bd6ec360e2
ad9081_fmca_ebz/vcu118: Set XCVR params for 204C link
...
Set XCVR parameter for 204C 24.75 Gbps with a dynamic range of 10Gbps..24.75Gpbs
Organize XCVR params based on lane rate
2021-05-14 15:39:40 +03:00
693c002668
ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd: Add 204C support for XCVR
...
Remove Xilinx PHY and simplify project
2021-05-14 15:39:40 +03:00
d92f925b06
ad9081_fmca_ebz: Disable XBAR from DAC TPL
2021-05-14 15:39:40 +03:00
77a5edaa83
scripts/adi_board.tcl: In 204C do not connect SYNC
...
Take link mode parameter from util_adxcvr, check it against the axi_adxcvr.
2021-05-14 15:39:40 +03:00
1db04a47b8
ad9083_evb: Update parameters to 10Gpbs lane rate
2021-04-19 13:21:34 +03:00
8335e1bd9a
sysid: Make sure gitbranch_string is always declared
...
Parsing of not existed "gitbranch_string" fails the build process.
2021-03-24 13:34:32 +02:00
6a374ef457
ad469x/zed: Add multicycle path constraint
2021-03-22 13:05:05 +02:00
40baa63f0f
adrv2crr_fmcomms8: Fix system_top.v
2021-03-19 17:56:28 +02:00
a1773c661c
adrv9009zu11eg_crr: Update spi
...
Add two more CS signals to P25 connector
2021-03-10 10:53:11 +02:00
3dce87d09b
ad9083: Add reference design for ad9083 eval board
2021-03-10 10:52:03 +02:00
dcec4fe1b7
adrv9001/zc706: Fix spaces
2021-03-10 10:35:52 +02:00
dc186645d8
adrv9001/zc706: Fix comments HPC to LPC
2021-03-10 10:35:52 +02:00
4a772265a9
Update Quartus Prime version from 19.3.0 to 20.1.0
...
adi_project_intel.tcl: Change quartus version to 20.1.0.
library: Set qsys version so that IP instances won't require a specific version.
2021-03-08 11:29:33 +02:00
1099badaf4
ad9082_fmca_ebz:zc706: Initial version
2021-03-05 15:54:23 +02:00
2213527f29
ad9082_fmca_ebz:zcu102: Initial version
2021-03-05 15:54:23 +02:00
f56e3c305b
ad9082_fmca_ebz:vcu118: Initial version
2021-03-05 15:54:23 +02:00
6b13b32f24
ad9081_fmca_ebz: Workaround DMA bug when bus size equals max burst size
2021-03-04 11:13:29 +02:00
677c154134
adrv9001/zcu102/cmos: Loosen up clock skew constraints to match LVDS settings
...
Set the same inter clock skew characteristics as used in LVDS mode. The
physical lanes/routes are common on both modes.
2021-03-04 11:13:10 +02:00
03de08609b
fmcomms2/zed: Disable unused TDD to save space and timing
2021-03-04 11:13:10 +02:00
0dd3173547
adrv9001/zc706: Initial commit
...
The project supports CMOS interface only.
VADJ on the ZC706 must be programmed to 1.8V
Instructions can be found here:
https://www.xilinx.com/Attachment/ZC706_Power_Controllers_Reprogramming_Steps.pdf
https://forums.xilinx.com/t5/Xilinx-Evaluation-Boards/ZC706-Doesn-t-work-with-VADJ-at-1-8v/td-p/430086
2021-03-03 09:03:03 +02:00
3be5137aec
cn0540/cora: Remove multicycle constraint
...
Design uses 80MHz spi_clk which does not require
special considerations
2021-02-18 14:14:16 +02:00
701e5f6515
scripts/adi_board.tcl: Add simulation support
...
This will allow building base test harnesses and place on top of them
existing block designs for simulation purposes.
Test harnesses will contain basic functionality like
- clock and reset generators
- AXI master to aid register access of the cores.
- memory model of the DDR
- interrupt controller
Existing procedures (ad_mem_hp0_interconnect, ad_cpu_interconnect, ... ) will
connect to this harness as they do to a real base design.
2021-02-12 16:21:10 +02:00
0374a7c1ac
ad9081_fmca_ebz/vcu118: Added common 204C use cases as example
2021-02-05 15:24:15 +02:00
ddd8a14790
ad9081_fmca_ebz: Remove system reset from Xilinx PHY
...
Reset in device clock domain caused timing failures.
Since link reconfiguration is not supported the reset is not required.
2021-02-05 15:24:15 +02:00
af3e1c7003
ad9081_fmca_ebz/a10soc: Np 12 support
2021-02-05 15:24:15 +02:00
f73ed741c9
fmcadc5: Connect link clock to second JESD link layer
2021-02-05 15:24:15 +02:00
3f2f88ebbc
ad_fmclidar1_ebz: Set bits per sample towards the DMA interface
2021-02-05 15:24:15 +02:00
dafdd1c1e9
ad9208_dual_ebz: Use ad_xcvrcon procedure to connect device clock
2021-02-05 15:24:15 +02:00
bb9eafceef
ad9081_fmca_ebz/zcu102: Add case analysis to select correct out clock frequency
2021-02-05 15:24:15 +02:00
d0f8a81b2f
ad9081_fmca_ebz: Np 12 support
...
204B functional
204C functional
2021-02-05 15:24:15 +02:00
454b900f90
jesd204: Xilinx: NP=12 support
...
To support deterministic latency with non-power of two octets per frame
(F=3,6) the interface width towards the transport layer must be resized
to match integer multiple of frames.
e.g Input datapath width = 4; Output datpath width = 6;
for F=3 one beat contains 2 frames
for F=6 one beat contains 1 frame
The width change is realized with a gearbox.
Due the interface width change the single clock domain core is split
in two clock domains.
- Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b
- lane rate / 20 for input datapath width of 8 octets 8b10b
- lane rate / 66 for input datapath width of 8 octets 64b66b
- Device clock : Link clock * input data path width / output datapath width
Interface to transport layer and SYSREF handling is moved to device clock domain.
The configuration interface reflects the dual clock domain.
If Input and Output datapath width matches, the gearbox is no longer
required, a single clock can be connected to both clocks.
2021-02-05 15:24:15 +02:00
7be66b63c1
adrv9009zu11eg:fmcomms8: Fix lane swapping for TX channels 0 and 1 on the FMCOMMS8
2021-02-05 15:07:09 +02:00
6d504d14cf
fmcomms8: zcu102: Fix lane swapping
2021-02-05 15:07:09 +02:00
0fd5590e56
ad9081_fmca_ebz: a10soc: Initial version
...
Parametrizable project with default profile of:
M=8 L=4 SampleRate=250 MSPS
LaneRate=10 Gbps
2021-02-05 10:24:59 +02:00
6e6c51dd27
common/a10soc: Bridge support
2021-02-05 10:24:59 +02:00
f0b753321a
common/intel: Add util_adcfifo integration script
2021-02-05 10:24:59 +02:00
3041e77659
ad40xx/zed: Update constraints
2021-02-04 11:04:32 +02:00
05469a011c
ad40xx/xilinx: Activate AXI_SLICE_SRC for the DMA
2021-02-04 11:04:32 +02:00
dd4c8d6807
adrv9001/zcu102: Add debug header
2021-01-26 15:22:41 +02:00
728904af09
adrv9001/zcu102: Run postRoutePhysOpt to close Rx1 to Rx2 path timing
2021-01-26 15:22:41 +02:00
bae7e48c50
adrv9001/common: Run DMAs @ 100MHz
2021-01-26 15:22:41 +02:00
f68c222489
cn0501/coraz7s: Fix sysid
2021-01-22 15:40:37 +02:00
bb44e5399f
adrv9001/zed: Connect TDD sync to PMOD JA1
2021-01-20 13:00:01 +02:00
3918d43cd1
adrv9001/zcu102: Add TDD sync to PMOD0 J55.1
2021-01-20 13:00:01 +02:00
fe9f72db9c
adrv9001/common: Export TDD mode signal
2021-01-20 13:00:01 +02:00
18b2a8b0a7
adrv9001/zed: Add TDD support
2021-01-20 13:00:01 +02:00
0c2745361b
adrv9001/zcu102: Add TDD support
2021-01-20 13:00:01 +02:00
6f2f2b8626
makefile: Regenerate make files
2021-01-20 01:02:56 +02:00
da61515d41
ad40xx: Fix bd.tcl script
2021-01-20 01:02:56 +02:00
acbbd4636a
sysid: Upgrade framework, header/ip are now at 2/1.1.a
...
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
da9828a63e
ad9081:zcu102: Expose parameters to environment
...
Allow setting project parameters from the environment.
2021-01-19 17:10:08 +02:00
235fb4859a
usrpe31x: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
f1421c91ee
sidekiqz2: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
f68393ecb9
adrv936x: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
3e237459e3
pluto: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
d9639db991
m2k: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
e41ba7f6f5
adrv9009zu11eg: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
9ec3408c79
adi_project_xilinx: Fix the adi_project process
...
In most of the standalone projects the generic project creation flow is not followed. The project's device
is defined manualy. This fix makes sure that those projects still builds without an issue.
NOTE: In these case we should use adi_project_create directly in system_project.tcl.
2021-01-15 15:26:43 +02:00
b9ac8df503
project-xilinx.mk: Add *.hbs to clean list
2021-01-15 13:50:53 +02:00
067b57d404
vc707: Fix mdio intf
2021-01-15 13:50:53 +02:00
c54552d823
adi_project_xilinx: Add env var
...
add ADI_DISABLE_MESSAGE_SUPPRESION which disables
adi_xilinx_msg.tcl
projects/scripts/adi_project_xilinx.tcl
2021-01-15 13:50:53 +02:00
ead4513ad6
adi_xilinx_msg: Downgrade Synth 8-2490
2021-01-15 13:50:53 +02:00
51b5e4f58b
tcl: Change Vivado version to 2020.1
...
handoff is now exported as .xsa
2021-01-15 13:50:53 +02:00
fbb2a0e1a0
de10nano: Add hps_conv_usb_n signal to stabilize UART lines
...
Without defining this signal, the UART lines receive garbage data
when no cable is connected to the J4 USB UART port.
The GPIO9 is enabled in the reference base design along with the
4MA CURRENT_STRENGTH constraint on the UART pins
2021-01-13 15:36:45 +02:00
dee108ba22
fmcomms8/intel: Fix fPLL configuration
...
When phase alignment is active, the PFD frequency value should be used
as outclk1 actual frequency.
The configuration interface of the fPLL does not support fractional values.
If the reference clock is fractional, the tool will throw an error that requirement
above is not respected.
Round up the reference clock for the SERDES and the lane rate in order to
overcome this issue, until it's not fixed by Intel.
2021-01-12 19:34:44 +02:00
85f5dc8230
ad9371x/intel: Fix fPLL configuration
...
When phase alignment is active, the PFD frequency value should be used
as outclk1 actual frequency.
The configuration interface of the fPLL does not support fractional values.
If the reference clock is fractional, the tool will throw an error that requirement
above is not respected.
Round up the reference clock for the SERDES and the lane rate in order to
overcome this issue, until it's not fixed by Intel.
2021-01-12 19:34:44 +02:00
d539a8119c
adrv9009/intel: Fix fPLL configuration
...
When phase alignment is active, the PFD frequency value should be used
as outclk1 actual frequency.
The configuration interface of the fPLL does not support fractional values.
If the reference clock is fractional, the tool will throw an error that requirement
above is not respected.
Round up the reference clock for the SERDES and the lane rate in order to
overcome this issue, until it's not fixed by Intel.
2021-01-12 19:34:44 +02:00
bab3426f91
scripts: allow directly specifying a device when creating a project
...
Add a layer under adi_project that allows you to directly specify a device/board combination without determining it from the project name.
2021-01-12 14:13:07 +02:00
b989ba36d1
axi_spi_engine: Fix util_axis_fifo instance related issues
2021-01-08 12:29:26 +02:00
5c87e5b1a7
cn0501: Initial commit for Coraz7s
2020-12-18 14:05:56 +02:00
71009e74ff
ad7768_if: Remove buffers, add parallel data path
2020-12-15 15:16:14 +02:00
fa67eb5532
adv7513_de10nano: Fix gpio_bd assignments
2020-12-08 14:38:04 +02:00
e331abedc6
common/de10nano: Cosmetic updates only
2020-12-08 14:38:04 +02:00
8d378c56bf
common/de10nano: Full HD 60 FPS support
...
-change the video memory interfacing from f2h_axi_slave to
f2h_sdram0
- add f2h_sdram1 port as the default interface for converter DMA
- set as default the full HD resolution at 60 FPS (pixel clock 148.5MHz)
- use a second 200MHz(198MHz) clock from the pixel_clk_pll, as DMA source
to destination clock.
2020-12-08 14:38:04 +02:00
3dd370a27c
ad9081_fmca_ebz: enable xbar in DAC TPL
2020-11-27 09:45:11 +02:00
ad755788a0
ad9081_fmca_ebz/zc706: Initial version
...
M=8 L=4 SampleRate=250 MSPS
LaneRate=10 Gbps
2020-11-12 15:46:27 +02:00
e9f319e3d7
ad9081_fmca_ebz: HP0 is already initialized in ZC706
...
On carriers like ZC706 the HP0 interconnect is in already in use so it must
not be initialized here.
2020-11-12 15:46:27 +02:00
b080b52a14
daq3:zcu102: Connect overflow pins for the AD9680 TPL
2020-11-11 14:24:02 +02:00
2799777657
adrv9009zu11eg/adrv2crr_fmc: Fix hmc7044_car_gpio connections
2020-11-11 07:07:29 -05:00
ecd880d44c
adrv9009zu11eg:fmcomms8: Fix SPI timing constraint
2020-11-05 17:42:41 +02:00
685ca91f19
ad_fmclidar1_ebz/a10soc: Fix a typo
...
Fixing a typo in projects/ad_fmclidar1_ebz/a10soc/system_top.v.
2020-11-05 12:53:50 +02:00
2ff5420630
Update system_top.v
...
Add a comment that the spi CS decoding is tied to a setting in the device tree.
2020-11-02 16:59:08 +02:00
78b2ae02a1
ad9434_fmc,ad9467_fmc,fmcadc5: Update projects to use ad_iobuf, not IOBUF
2020-11-02 16:13:35 +02:00
a3a610728c
intel: Update projects to use ad_iobuf instead of ALT_IOBUF
2020-11-02 16:13:35 +02:00
ae7ec82334
adrv9009zu11eg: Update spi module to use generic verilog
2020-11-02 16:13:35 +02:00
9093a8c428
library: Move ad_iobuf to the common library, as it's not Xilinx specific
...
Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
912e09ad18
m2k: Add DAC last sample connections
2020-11-02 15:50:12 +02:00
d676cfd64f
adv7513/de10nano: Define the USB clock
2020-10-30 10:55:01 +02:00
c048a9243a
de10nano: Fix IO assignments
...
- define IO assignments for HPS SPI master
- delete unused GPIO ports
2020-10-30 10:55:01 +02:00
7cc5716ea8
ad469x: Remove sysid custom string init
2020-10-28 11:31:50 +02:00
5359d991b2
ad469x_zed: Update bd.tcl with new port names
2020-10-28 11:31:50 +02:00
ad4adddbe5
ad469x_fmc: Minor cosmetic update on the config file
2020-10-27 10:09:50 +02:00
0644edb389
fmcomms8: a10soc: Move RX and Observation to second SDRAM interface
...
This is an attempt to get full bandwidth without a FIFO
2020-10-26 18:12:14 +02:00
3a5097875f
common: a10soc: Allow for the second SDRAM interface to be used at a different clock
2020-10-26 18:12:14 +02:00
6621fbec61
fmcomms8: a10soc: Initial commit
2020-10-26 18:12:14 +02:00
35e4eb6a7b
ad469x: Add reference design for ad469x eval board
2020-10-22 19:17:10 +03:00
83cebe899f
daq3: Update projects to the new TPL
...
Also modified the FIFO ports to have the same widths so that in a
future commit the bypass would be available for cases when the
sampling rate won't be the maximum rate or the number of channels
active will be less than maximum number of channels
2020-10-21 18:59:37 +03:00
9f58b465ea
adaq7980: Add AXI pulse generator to generate the offload trigger
2020-10-21 09:59:26 +03:00
37254358dd
makefile: Regenerate make files
2020-10-20 12:51:10 +03:00
1f6bba0aa1
ad77681: Add axi_clkgen ip for spi engine
...
spi_clk changed from 40MHz to 80MHz
2020-10-19 10:42:21 +03:00
d6b23d5149
scripts/adi_pd_intel: Delete noisy print outs
2020-10-17 08:02:33 +03:00
66672932d5
adv7513/de10nano: Fix connection of ltc2308 SPI's interface
2020-10-14 10:37:14 +03:00
72635d73e3
cn0540: Add axi_clkgen to Makefile
2020-10-14 00:05:57 +03:00
9364c8501a
adrv9009_zu11eg: Add synchronization at application layer
...
Switch RX path reset to be controlled by the TPL and use
RX SYSREF as external synchronization for the ADC TPL
Use TX SYSREF for synchornizing the TX DDS
2020-10-07 09:04:21 +03:00
4026eaa19b
ad9081_fmca_ebz: Fix device clocks termination
...
The device clocks are AC coupled LVDS lines without external termination.
For proper operation internal differential termination must be enabled,
the DQS_BIAS will DC bias the AC coupled signal to VCCO/2 (1.8/2) 0.9V
2020-10-06 16:13:21 +03:00
1c208c01d6
ad9656:Add reference design for the ad9656 eval board ( #494 )
...
Added reference design for the ad9656 evaluation board coupled with the
zcu102 carrier board. The JESD204 communication link that transfers data
from the 4 ADCs to the FPGA has the following paramenters : L=4, M=4, S=1,
F=2, HD=0, N=16, NP=16. The JESD204 line rate is configured to be 2.5GHz.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2020-10-06 09:53:40 +03:00
23cd6d2f91
sysid: Remove cstring init string
...
These two projects were originally missed by the find/replace command
2020-10-02 23:34:40 +03:00
da6d9da4f0
projects: cn0540: coraz7s: Add XADC support
...
The coraz7s has an Arduino/chipKIT Shield connector with 6 Single-ended
and 8 Differential Analog inputs tied to Xilinx's XADC.
The CN0540 uses the A0-5 pins as single-ended ADC channels to monitor
the differential input, ADC driver, and buffer voltages.
Signed-off-by: Sergiu Cuciurean <sergiu.cuciurean@analog.com>
2020-10-02 11:14:21 +03:00
11822e2824
cn0540/coraz7s: Set and input delay of one spi_clk cycle for the MISO line
...
Note, the current SCLK to spi_clk ratio is four. That means, the input
delay in the MISO line is 25% of the SCLK period.
If the SCLK to spi_clk ratio is changing, this constraint must be
updated.
2020-10-02 10:50:06 +03:00
dae1de0405
cn0540/bd: Generate a 80MHz spi_clk
...
Generate a higher frequency of spi_clk using an axi_clkgen. (MMCM)
CAUTION: ad7768-1 is still violating the standard SPI timing,
reducing the timing window significantly for the last bit (or last high
bit).
2020-10-02 10:50:06 +03:00
c656a2e29b
sysid: Initialize parameter
2020-09-30 19:12:24 +03:00
d8ab27b2af
sysid: Remove cstring init string
2020-09-30 19:12:24 +03:00
bd2126fd2f
cn0363: Remove iobuf for spi sdo
...
iobuf was generating drc warning because it was not fully connected.
2020-09-25 16:40:41 +03:00
9c827d6b03
cn0540/de10nano: Ignore 15003 critical warning
...
Ignore the following critical warning on DMAC instance:
Critical Warning (15003): "mixed_port_feed_through_mode" parameter of RAM atom
system_bd:i_system_bd|axi_dmac:axi_dmac_0|axi_dmac_transfer:i_transfer| \
dmac_request_arb:i_request_arb|dmac_dest_mm_axi:i_dest_dma_mm| \
altsyncram:bl_mem_rtl_0|altsyncram_0tp1:auto_generated|ram_block1a1
cannot have value "old" when different read and write clocks are used.
2020-09-25 12:56:53 +03:00
9cac38017b
daq2/a10soc: Set optimization mode to high performance effort
2020-09-25 12:56:14 +03:00
230c579339
common/s10soc: Input ports do not have a current strength property
2020-09-25 12:56:14 +03:00
5644907f75
adi_intel_msg: Dissable "unused TX/RX channel" critical warning for Stratix 10
2020-09-25 12:56:14 +03:00
a738879fa0
ad77681evb: Remove redundant ad_data_clk
2020-09-25 12:20:41 +03:00
144fcc2965
adrv9009: Fix typo for number of samples calculation for observation channel
2020-09-25 11:58:58 +03:00
bde2d1d66d
fmcomms8: zcu102: Leave the SPI constraint at 25 MHz
2020-09-25 11:54:12 +03:00
4d2e05d5dd
fmcomms8: common: In the SPI module, use ad_iobuf instead of a Xilinx primitive
2020-09-25 11:54:12 +03:00
f8c2eb12d4
fmcomms8: zcu102: Remove the test pins, as they are not connected
2020-09-25 11:54:12 +03:00
1e31b9dd97
arradio: Remove unused signals
...
Remove 'ad9361_clk_out' since is not used anymore, fixing in this way 'Warning (21074): Design contains 1 input pin that do not drive logic'
2020-09-23 09:16:48 +03:00
f2f6422751
sysid: Fix board/project name underscore issue
2020-09-17 10:32:58 +03:00
6ae822d42c
cn0506_rmii: Fix no defined clock warnings
2020-09-16 10:57:15 +03:00
49d4286459
cn0540/de10nano: Delete GPIO connection to DRDY
2020-09-15 18:14:23 +03:00
4838ac0ac2
cn0540/coraz7s: Time the SPI interface of AD7768-1
2020-09-15 18:14:23 +03:00
0933949ad7
adv7513: Add initial project for de10nano
2020-09-15 18:14:23 +03:00
043ddbaf9f
cn0540: Add de10nano reference design
2020-09-15 18:14:23 +03:00
ad8d2d225f
de10: Delete redundant base design
2020-09-15 18:14:23 +03:00
fd1c3c7cdd
common/de10nano: Add de10nano base design
2020-09-15 18:14:23 +03:00
6cea8ce777
adi_project_intel: Add de10nano support
2020-09-15 18:14:23 +03:00
40772a8b2c
ad40xx_fmc/zed: Fix constraints, to avoid critical warnings in synthesis
2020-09-15 13:08:39 +03:00
3241924d14
sysid_intel: Added sysid to intel projects
2020-09-11 15:46:06 +03:00
f57643b451
sysid_intel: Added adi_pd_intel.tcl
2020-09-11 15:46:06 +03:00
0152b645a6
m2k: Fix Warnings
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Fix warnings caused by attempting to set a value to a disabled parameter.
2020-09-11 10:23:26 +03:00
9ee0f09078
daq3:qsys: Activate input pipeline stage for AD9680's JESD interface
2020-09-09 14:15:37 +03:00
c8e0a1ec04
projects: adrv9009: intel: Update JESD204 LANE_RATE and REFCLK_FREQUENCY
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To match the Linux default setup.
Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
2020-09-09 14:15:37 +03:00
61ece1f1e9
s10soc: Insert an additional bridge between DMA and HPS
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Due to the interface differences between HPS's AXI4 and DMA's AXI4, the
tool will try to automaticaly add some bridges between the two
interface. Unfortunatly it does generate timing issues at the f2sdram0
interface of the HPS instance. By explicitly instantiating an AXI
bridge, these timing issues disappears.
2020-09-09 14:15:37 +03:00
46b6bf8f8a
adrv9009/qsys: input pipline active for jesd204_rx and jesd204_rx_os
2020-09-09 14:15:37 +03:00
5a8f277253
adrv9009/s10soc: Add support for Stratix10 SOC
2020-09-09 14:15:37 +03:00
2b5136db98
scripts/project_intel.mk: Update CLEAN targets
2020-09-09 14:15:37 +03:00
eb8e1142cd
adrv9009/intel: Fix the register address layout
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The reconfiguration interface for the Stratix10 XCVR has a different
address width. Prepare the register map layout of the project to support
this new architecture.
2020-09-09 14:15:37 +03:00
8818089015
a10soc: Reconfiguration interface address width improvement
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The reconfiguration interface's address width is different in various
architectures. Define the required address width in system_qsys.tcl.
2020-09-09 14:15:37 +03:00
91b199a907
s10soc: Add new feature for ad_cpu_interconnect
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If we have a lot of peripherals connected to the CPU's memory interface,
the generated interconnect can grow to much decreasing the timing
margin.
One solution is to group the peripherals by its interface types and
functions and use bridges to connect them to the memory interface.
This commit adds the possibility to insert an Avalon Memory Mapped
bridge when we create the connection between the peripheral and CPU.
Should be used just with Avalaon Memory Mapped interfaces.
2020-09-09 14:15:37 +03:00
f9c4283f45
stratix10soc: Initial commit of base design
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Note: Currently we have a engineering sample version 2 board.
2020-09-09 14:15:37 +03:00
24090fafd8
adrv9001/zcu102: Loopback VADJ error to the FMC board
2020-08-31 14:14:03 +03:00
d14376547f
adrv9001/zed: Refactor VADJ test in VADJ error
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The ADRV9002 uses in the digital interface 1.8V, however the Zed VADJ is
selectable by a jumper can go up to 3.3V . Voltage levels higher than 1.8V
are detected by the EVAL-ADRV9002 board, asserting the VADJ_ERR pin.
If VADJ error is set high keep all drivers in high-z state and signalize
it to the software layer through a gpio line.
2020-08-31 14:14:03 +03:00
72f916fcf5
adrv9001/zcu102: Update interface signal names based on direction
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Let the names of signals from source synchronous interface match the
direction of the signals.
2020-08-28 13:23:00 +03:00
a212ad6e58
adrv9001/zed: Update interface signal names based on direction
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Let the names of signals from source synchronous interface match the
direction of the signals.
2020-08-28 13:23:00 +03:00
eb2f211d30
scripts/intel: Add message severity definition file
2020-08-25 14:46:52 +03:00
9c4df588bb
fmcomms2: a10soc remove project
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Starting from Quartus 18.1 the project won't build as LVDS SERDES needs to be
driven by a dedicated reference clock pin and A10SOC doesn't have dedicated pins
routed at the _CC FMC location.
Prior to version 18.0 this was reported as a critical warning.
See https://community.intel.com/t5/Intel-Quartus-Prime-Software/LVDS-SERDES-reference-clock-enforcement-change-in-18-1/td-p/196078
2020-08-25 14:19:48 +03:00
118e1f9e8b
adrv9001/zed: Initial support for Zed
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CMOS only support for ADRV9001 on ZedBoard
2020-08-24 17:49:12 +03:00
b27f3ac18f
adrv9001:zcu102: Initial version
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Generic project that supports CMOS or LVDS interface for the ADRV9001 transceiver.
2020-08-24 17:49:12 +03:00
d8c98c9904
cn0540/coraz7s: Relax timing in SPI Engine
2020-08-24 16:45:02 +03:00
fa0b39fa20
adi_project_intel: Update QSYS generation
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In Quartus Prime in place of the set_domain_assignment command, the
set_interconnect_requirement command is used.
2020-08-17 12:02:49 +03:00
b54effc9c9
daq2/a10gx: Set optimization mode to aggressive performance
2020-08-17 10:43:03 +03:00
fb7da01498
adrv9371x/a10gx: Set optimization mode to aggressive performance
2020-08-17 10:43:03 +03:00
738f7af23b
ad40xx_fmc: SDI delay should be set to 1
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In general we have to add a delay of half SCLK cycle.
(latch the MISO on the next consecutive SCLK edge)
2020-08-13 10:01:16 +03:00
4766d01915
m2k: Update constraints
2020-08-13 07:01:19 +03:00
4d39a3595f
m2k: Connect signals for instrument sync
2020-08-13 07:01:19 +03:00
f3b69c15c9
scripts/intel: Update version check
2020-08-12 10:33:29 +03:00
218f45a0df
scripts/intel: Set supported Quartus version to 19.3
2020-08-12 10:33:29 +03:00
62eb5a067d
fmcomms2/a10soc: Unused outputs should be left hanging
2020-08-11 10:14:18 +03:00
a66029aef3
adrv9009/a10gx: Delete redundant timing constraints
2020-08-11 10:14:18 +03:00
02ada3bbf7
a10gx: Delete input/output delay definitions
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All input and output delays should be referenced to a virtual clock.
If the input and output delays reference base clocks or PLL clocks rather than
virtual clocks, the intra- and inter-clock transfer clock uncertainties,
determined by derive_clock_uncertainty, are incorrectly applied to the I/O ports.
See mnl_timequest_cookbook.pdf for more info.
2020-08-11 10:14:18 +03:00
f1a0946a5d
daq3: Delete redundant timing constraint
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Delete none generic timing constarints related to the memory interface.
Set optimization mode to default.
2020-08-11 10:14:18 +03:00
1c907b9248
daq2/a10gx: Use the default optimization mode
2020-08-11 10:14:18 +03:00
9043f3737b
Revert "a10gx: Optimise the base design"
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This reverts commit 9afc871b70
2020-08-11 10:14:18 +03:00
4af0c98c56
a10gx: Fix exceptionSlave interface definition for HPS
2020-08-11 10:14:18 +03:00
5ba3448987
scripts/project-intel: Update CLEAN target
2020-08-11 10:14:18 +03:00
0b51c474a1
a10gx: Add a Avalon Pipeline Bridge between EMIF and DMA's
2020-08-11 10:14:18 +03:00
6d19041b21
dac_fmc_ebz: QPRO is using apply_instance_preset
2020-08-11 10:14:18 +03:00
0de5039b96
avl_dacfifo: add_intance command must have a version attribute
2020-08-11 10:14:18 +03:00
8fd1ad64d6
quartus: Increase tool version to 19.2
2020-08-11 10:14:18 +03:00
f3142a6a7a
adi_project_intel: set_interconnect_requirment command is deprecated
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Use set_domain_assignment to set up the maximum pipeline stages for the
main interconnect.
2020-08-11 10:14:18 +03:00
a39fa831d0
ad9371:a10gx: Relax interconnect requirements
2020-08-11 10:14:18 +03:00
7e22f91429
adrv9371:a10gx: Remove constraint from DDR
2020-08-11 10:14:18 +03:00
359e5d94ec
a10gx: Remove constraint from eth_ref_clk
2020-08-11 10:14:18 +03:00
967a138d0f
adi_project_intel: Add support for Quartus Pro
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By defualt the supported tool chain is Quartus PRO. If you want to
build the project with Quartus Standard, you need to define an environment
variable called QUARTUS_PRO_ISUSED with the value 0. (e.g. export
QUARTUS_PRO_ISUSED=0 )
Note: Not all projects going to build on Quartus Standard, you should
fix the errors if there is any.
2020-08-11 10:14:18 +03:00
054193e083
adi_project_intel: Delete all MESSAGE_DISABLE assignment
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These kind of assignments should be placed into file like
~/projects/scripts/adi_xilinx_msg.tcl
2020-08-11 10:14:18 +03:00
4ca1311d57
quartus_pro: Global assignment ENABLE_ADVANCED_IO_TIMING is not supported
2020-08-11 10:14:18 +03:00
8d6b8fc631
Add cn0506_rmii/zcu102 support on revB
2020-08-10 18:32:44 +03:00
7e96514230
Add cn0506_rmii/zc706 support on revB
2020-08-10 18:32:44 +03:00
321b82398b
Add cn0506_rmii/zed support on revB
2020-08-10 18:32:44 +03:00
6c2b1b1634
fmcomms5/zc702: Fix the sys_dma_clk connections
2020-06-19 12:53:18 +03:00
137c31db1d
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-18 15:45:19 +03:00
299273f5a1
daq2/intel: Update project to use generic JESD204B TPL
2020-06-18 15:45:19 +03:00
847f0f22e6
cn0540: Fix typo
2020-06-04 18:38:14 +03:00
193fce338d
cn0540: Initial commit
2020-05-28 18:49:35 +03:00
03ab28d7bf
ad77681evb: Remove coraz7s project
2020-05-28 18:49:35 +03:00
71d500bdd4
adrv9009/intel: Use generic TPL cores
2020-05-26 16:22:30 +03:00
9c8190f709
adi_project_xilinx.tcl: discover all timing failures
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Look for an overall indicator of timing failure.
Create critical warning if timing is failed.
2020-05-26 14:47:38 +03:00
47a97aac7c
adrv9371x/intel: Update project to use generic JESD204B TPL
2020-05-25 11:55:40 +03:00
e8f6523197
ad9081_fmca_ebz: adapt to renamed tpl core
2020-05-20 19:08:25 +03:00
db6af63583
scripts/adi_env.tcl: print in logs system variables are used
2020-05-20 19:07:23 +03:00
e7600eb552
ad7616_sdz: Fix the project, after SDI ports were merged
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Update the project to support the SDI port merge patch: 4d54c7e
2020-05-20 11:44:22 +03:00
4d54c7e2d6
spi_engine_execution: Merge the SDI lines into one vector
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This modification will help to support multiple SPI engine
execution setups (e.g. different NUM_OF_SDI) for the same project.
2020-05-19 09:28:02 +03:00
6535e5b2ba
scripts/xilinx: Version mismatch is upgraded to ERROR
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There is a major compatibility issue between 2019.1 and 2019.2.
The file system_top.hdf got a different file extention. This will
cause a compilation failer in the end of the build. To save time
and fail earlier, upgrade the version mismatch message to ERROR.
If user still wants to build a branch with different tool version
the variable ADI_IGNORE_VERSION_CHECK should be set to 1.
2020-05-15 12:16:35 +03:00
Laszlo Nagy
vladimirnesterov
Sergiu Arpadi
stefan.raus
Adrian Costina
Istvan Csomortani
aholtzma
AndreiGrozav
IMoldovan
hotoleanudan
Sergiu Cuciurean
Stanca Pop
Stanca.Pop
Dragos Bogdan