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221 Commits (c8a095f79cd807e69ec8ac01f33ca6ca30e88509)

Author SHA1 Message Date
Istvan Csomortani fbafaa8507 MicroBlaze base system: Fix a few net names 
Every interconnect interface net name follows the convention:
	<interconnect name>_<interface name>
	No changes in logic or any connection!
 2014-04-01 10:40:35 +03:00
Adrian Costina a881557645 base_design: Fixed AC701 and VC707 contstraints 
AC701: Modified the IOSTANDARD for some of the pins to correspond to the
AC701 user guide.
VC707: Fixed naming for some system clocks
 2014-03-31 17:38:20 +03:00
Istvan Csomortani f9a67371c0 Zynq Base System: Reset is synchronized to lowest system clock 
System reset (sys_100m_reset) is synchronized to lowest system
	clock (FCLK0), via a Processor System Reset module
 2014-03-26 17:58:14 +02:00
Istvan Csomortani 0f10623be4 AC701/VC707: Define common variables 
Define variables sys_zynq, sys_mem_size, sys_addr_cntrl_space.
 2014-03-25 14:24:51 +02:00
Istvan Csomortani aa7b0bb4dd VC707 basesys: General fixes, actual status: working 
- Add an auxiliary cpu interconnect
	- Add an auxiliary interrupt concatenation module
	- Add new MIG file, current frequency of the DDR interface is 100
	  Mhz
	- Memory interconnect optimisation strategy is 'Maximize
	  Performance'
 2014-03-24 13:07:48 +02:00
Istvan Csomortani b94acf78aa AC701 bases sys: Add an auxiliary cpu interconnect 
- Add an auxiliary cpu interconnect, the KC705 base system was
	  used as reference
	- Base system is tested and working
 2014-03-24 13:01:52 +02:00
Istvan Csomortani 792e8a208d KC705 base system: Make a few cosmetic changes 2014-03-24 12:55:37 +02:00
Istvan Csomortani 8a08031dce AC701: Modify interrupt concatenation 
- Interrupt concatenation is the same as in case of KC705
 2014-03-24 10:20:56 +02:00
Istvan Csomortani 13b4dd07d0 KC705 base system: Modify interrupt concatanation 
- Add an aditional interrupt input net for the sys_concat_aux_intc
	  module
 2014-03-21 14:45:18 +02:00
Istvan Csomortani c6143dbfaf KC705 base system: Delete trailing whitespaces. 2014-03-21 14:42:27 +02:00
Istvan Csomortani 3a0d1282b7 Fix the remaining issues 
- Swap the IO locations of ports vsync and hsync
	- Change the mem_interconnect optimization strategy to Maximize
	  Performance
 2014-03-20 14:36:01 +02:00
Istvan Csomortani 7cdab9b5b0 Change the internal clock generator to Clock Wizard 
- Using a Clock Wizard Module, in place of the DDR Controler's MMCM for internal clock
	  generation.
 2014-03-18 17:24:45 +02:00
Rejeesh Kutty dc44703cf1 zynq/non-zynq: identical signal names and instances 2014-03-17 17:02:03 -04:00
Rejeesh Kutty a6da4ca01c zynq/non-zynq merge variables 2014-03-17 16:39:52 -04:00
Rejeesh Kutty e1f23e7d49 Merge branch 'master' of github.com:analogdevicesinc/hdl 2014-03-11 09:58:34 -04:00
Rejeesh Kutty f3ae57a53e global clock and reset names 2014-03-11 09:57:59 -04:00
Istvan Csomortani 75963ab376 Initial check in of VC707 base project 
- All source files for the VC707 base project
	- Update the common base system to the new naming convention
 2014-03-10 17:26:17 +02:00
Rejeesh Kutty 5c3b65d01b adv7511: kc705/ac701 updates 2014-03-06 09:36:50 -05:00
Rejeesh Kutty 360f10395a initial checkin 2014-03-03 13:42:25 -05:00
Rejeesh Kutty 3c0ea759a0 changed path settings 2014-03-03 10:06:02 -05:00
Rejeesh Kutty ddac1a8834 added common board files 2014-02-28 21:17:01 -05:00