Commit Graph

453 Commits (c9206433b54d8ec81e2ff740fb0c888381d793fc)

Author SHA1 Message Date
Lars-Peter Clausen c9206433b5 adi_ip.tcl: Allow to specify processing order for adi_ip_constraints
In order to be able to use get_clocks in a constraint file the constraint
file needs to run after the constraint file that creates the clock. Allow to
specify the processing order when adding a constraint file to a core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:15 +02:00
Lars-Peter Clausen 24df683a2a axi_dmac: Disable src_response_fifo for now
The result of the src_response_fifo is currently not used so disable it for
now.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:12 +02:00
Lars-Peter Clausen 4062aa2860 util_axis_fifo: Fix reset signal
Some of the synchronizers were using the wrong reset signal, fix this.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:11 +02:00
Lars-Peter Clausen 762fa3290b util_axis_fifo: Add room and level outputs
Add a room output on the input side that reports how many free entries the
FIFO has and a level output on the output side that reports how many valid
entries are in the FIFO.

Note that the level output is only accurate if the output of the FIFO is not
registered, otherwise it might be off by one.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:09 +02:00
Lars-Peter Clausen ae4e7a0c37 util_axis_fifo: Add option to disable registered output
Add a option to specify whether the FIFO should have a registered output
stage or not. This is useful if the user wants to implement that stage
itself.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:08 +02:00
Lars-Peter Clausen f6594e276e Bring back AXIS FIFO as a separate module
Bring back the AXIS FIFO as a separate module instead of embedding it into
the DMAC module. This makes it possible to use it in other modules outside
of the DMAC.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:06 +02:00
Lars-Peter Clausen 8fc4b0630e util_axis_resize: Fix typo
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:04 +02:00
Rejeesh Kutty cb98e3e151 adcfifo: unused process 2015-04-13 13:31:50 -04:00
Adrian Costina 95e41e50a6 axi_dmac: Make all clocks asynchronous 2015-04-11 12:04:55 +03:00
Adrian Costina 7d22399860 util_axis_resize: Fixed makefile 2015-04-09 18:06:56 +03:00
Adrian Costina e9bd4b3512 axi_dmac: Updated altera core dependency, changed fifo files location 2015-04-09 17:58:21 +03:00
Adrian Costina 780455d68c Makefile: Updated makefiles. Added makefiles for altera 2015-04-09 17:57:06 +03:00
Istvan Csomortani b7d8e38c94 util_dacfifo: General update
+ Clean out the code, delete unnecessary flops
+ Add support for channel count (C_CH_CNT)
+ FIFO write (data from DMAC/upack) : valid just when xfer_req is asserted, address is free running, new xfer_req resets the address
+ FIFO read (data to DAC) : free running, reads to max address
2015-04-09 11:43:37 +03:00
Lars-Peter Clausen 668b8bda62 util_axis_resize: Add support for specifying the endianness
Add support for specifying whether the lsb of the larger bus are mapped to
the first or the last beat on the smaller bus.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 15:55:17 +02:00
Lars-Peter Clausen f1eb1c6064 util_axis_resize: Add support for non power-of-two ratios
Update the axi_repack core so it can handle non power-of-two ratios between
the input and output stream width. The ratio still needs to be a integer
though.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 15:55:17 +02:00
Lars-Peter Clausen b6458f9aab axi_dmac: Move axi_repack block to its own module
Move the axi_repack block to its own module. This allows it to use it
outside of the DMA controller.

Also rename it to util_axis_resize to better reflect its function.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 15:55:17 +02:00
Lars-Peter Clausen 8a47d0f94b adi_ip: Add helper function to add dependency to a IP core
Add a helper function that allows to add dependencies to IP cores to the
current IP core, this makes it possible to use a module from the other IP
without having to add the file itself to the current core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 15:52:41 +02:00
Lars-Peter Clausen 88abf98bd6 adi_env.tcl: Make default ad_hdl_dir path detection more robust
Instead of using a path relative to the current working directory use a path
relative to the location of the adi_env.tcl script.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 14:43:56 +02:00
Lars-Peter Clausen bdaad46704 axi_dmac: Remove up_write signal
up_write is just an alias for up_wreq these days. Just always use the later
and remove the former.
2015-04-08 14:43:56 +02:00
Lars-Peter Clausen 98609527e3 axi_i2s: Add I2S interface definition
Using interface definitions makes it possible to group pins of a peripheral
into a interface pins. This allows us to use connect_bd_intf_net to connect
all pins of the interface instead of having to manually call connect_bd_net
for each for the pins.

Using interface pins also unclutters the connections in the Vivado block
design view a bit.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
Lars-Peter Clausen 86e6f67d4b util_i2c_mixer: Add I2C interface
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
Lars-Peter Clausen fa696adc98 util_dac_unpack: Add fifo_wr interface
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
Lars-Peter Clausen 978f41cbe8 util_adc_pack: Add fifo_wr interface
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
Lars-Peter Clausen 6ba0667939 axi_dmac: Add fifo_wr/fifo_rd interfaces
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
Lars-Peter Clausen c82b186610 Add interface definitions for the fifo_rd and fifo_wr interfaces
Using interface definitions makes it possible to group pins of a peripheral
into a interface pins. This allows us to use connect_bd_intf_net to connect
all pins of the interface instead of having to manually call connect_bd_net
for each for the pins.

Using interface pins also unclutters the connections in the Vivado block
design view a bit.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
Lars-Peter Clausen 11cc18be79 adi_ip.tcl: Initialize ip_repo_paths
Initialize ip_repo_paths so that when building a peripheral we have access to the interface definitions stored in the repository.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
Lars-Peter Clausen d17cd22ef1 adi_ip.tcl: Allow to directly specify the vlnv string for adi_add_bus()
Modify the adi_add_bus() function to take the full vlnv strings instead of just the bus type.

This makes the function more flexible and e.g. allows to handle buses from other vendors.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
Rejeesh Kutty 0d0c15df98 axi_adcfifo: fix file names 2015-04-07 16:40:52 -04:00
Rejeesh Kutty 5f8e9a74ea makefile: updated 2015-04-07 16:32:01 -04:00
Rejeesh Kutty 922ea7fb34 util_sync_reset: removed 2015-04-07 16:28:05 -04:00
Rejeesh Kutty 6d0a2bf64c axi_adcfifo: added 2015-04-07 16:21:39 -04:00
Rejeesh Kutty e73e563a02 util_adcfifo_axi: removed 2015-04-07 16:16:51 -04:00
Rejeesh Kutty 712becd57f adcfifo: axi version 2015-04-07 16:16:17 -04:00
Rejeesh Kutty 4f7f109056 util_adcfifo: added 2015-04-07 16:08:38 -04:00
Rejeesh Kutty dfaa6f6571 fifo2s: removed 2015-04-07 16:01:36 -04:00
Rejeesh Kutty 3c316efbc5 fifo2dac: removed 2015-04-07 16:01:21 -04:00
Rejeesh Kutty 69cadd46ed adcfifo_axi: added 2015-04-07 16:00:47 -04:00
Rejeesh Kutty 056d6bbf40 dacfifo: added 2015-04-07 15:55:29 -04:00
Rejeesh Kutty 99c124e708 fifo2f: removed 2015-04-07 15:53:22 -04:00
Rejeesh Kutty 9098e3ebca fifo: removed 2015-04-07 15:52:31 -04:00
Rejeesh Kutty 86a70b3054 adcfifo: added 2015-04-07 15:43:02 -04:00
Rejeesh Kutty 7224ca1f0c dma: moved 2015-04-07 15:35:47 -04:00
Istvan Csomortani 9fa3131858 axi_fifo2dac: Initial commit
BRAM fifo for high speed DACs
2015-04-07 17:46:36 +03:00
Adrian Costina de2c3764d6 util_upack: Updated IP, added upack_valid and dma_xfer_in/dac_xfer_out ports. 2015-04-07 16:55:25 +03:00
Rejeesh Kutty 8af60576cd dma: constraints 2015-04-06 13:38:31 -04:00
Adrian Costina f79a152958 Makefiles: updated all makefiles adding clean functionality 2015-04-03 11:57:54 +03:00
Rejeesh Kutty ba2e635918 makefile: added 2015-04-01 16:28:20 -04:00
Rejeesh Kutty 2f41aebaa9 makefile: added 2015-04-01 16:28:19 -04:00
Rejeesh Kutty a5f937a96d makefile: added 2015-04-01 16:28:18 -04:00
Rejeesh Kutty 8b09fedae9 makefile: added 2015-04-01 16:28:16 -04:00