The introduction of sysid IPs on some Stratix 10 projects introduced a
problem where they would fail to build, due to mem_init_sys_file_path
not being defined. This is fixed now.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
* SPI Engine: fix early sdi data clear
In case an SPI read was immediately followed by a cs assert, the sdi
register was being cleared one cycle too soon, so that the data being
passed on was always 'b0.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Previous level-based trigger could cause issues in some low
sampling rate setups. This commit changes it to edge-based.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
The lack of the create_xgui_files causes Vivado to exit with an error
when running multiple Vivado instances (parallel make case)
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Set validation ranges for DATA_WIDTH and NUM_OF_CS for the expected
min/max values in the verilog source code.
Also, fix swapped description for CPHA in the documentation.
Signed-off-by: Carlos Oliveira <caosjr8@gmail.com>
Previously when issuing a load_config, each pwm channel
was stopped in its tracks and waited for an external sync,
if that was active, or load_config release.
The desired behaviour is to wait for the pwm channels to finish
their events from the current period, before a new aligned start.
Also, the first positive edge of each pulse was initiated only
in the second pwm channel period.
This niche behaviours have not affected any functionality in the
long term alignments for current setups.
Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
When leaving the offset equal to zero for a pwm
channel. That pwm channel was not waiting for all
channels to get in sync after a load config.
Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
Drop shell for loops in favor of makefile pattern rules,
so make can run targets in parallel using -j.
This doesn't affect Vivado's own settings.
As a benchmark, 12th Gen Intel(R) Core(TM) i9-12900H 5GHz(max):
$ make -C projects/adrv9009/zcu102/ clean-all
$ time make -C projects/adrv9009/zcu102/ -j$CORES lib
CORES=1:
real 9m27.223s
user 9m2.556s
sys 0m32.358s
CORES=8:
real 1m54.639s
user 16m26.512s
sys 1m2.317s
i.e. about 5 times faster to build IP core dependencies.
Signed-off-by: Liam Beguin <liambeguin@gmail.com>
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Replaces Symbolator with custom component diagram generator for more
reliable diagrams.
It uses the IP-XACT file, if it is not found, a placeholder is added
instead.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Import aiohttp and asyncio only when needed.
Better warning for unknown signals, params.
Use pattern matching in regmap parsing.
Fixup bundle count.
Add lists clarification to guidelines.
Enforce #1229 rules.
Clean-up Makefile.
Use non-breaking hyphen.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
1. Simplify the control logic by adding a state machine.
The improvements are on code readability and reliability.
2.Add a flush feature which can be used to clean the data from the DMA fifo.
This is useful when the DMA is programmed in cyclic mode and
data transmission is stopped by dma_transfer_suspend flag
The software intervention is reduced at setting the flag(dma_flush_en).
Flushing can also be done when activating the raw value with dma_flush_en active.
3. Add raw value support. Through this changes a user can set
the dac output to a fixed predefined value in the following two cases:
1. direct, without using the dma.
2. with dma, as a hold value. The fixed value will be kipped after a cyclic
buffer is stopped by axi_dac_interpolate, through dma_transfer_suspend
register/signal.
The raw value ca be set and transmitted independently on each channel.
The predefined value is stored in reg 0x19(0x64). For more details se
the documentation available at
https://wiki.analog.com/resources/fpga/docs/axi_dac_interpolate
axi_dac_interpolate - Remove last sample hold control
axi_ad9963 - Remove last sample hold control and set as default the
last sample hold functionality plus code optimization changes.
This commit introduces a different interface to submit transfers, using
DMA descriptors.
The structure of the DMA descriptor is as follows:
struct dma_desc {
u32 flags,
u32 id,
u64 dest_addr,
u64 src_addr,
u64 next_sg_addr,
u32 y_len,
u32 x_len,
u32 src_stride,
u32 dst_stride,
};
The 'flags' field currently offers two control bits:
- bit 0: if set, the transfer will complete after this last descriptor
is processed, and the DMA core will go back to idle state; if cleared,
the next DMA descriptor pointed to by 'next_sg_addr' will be loaded.
- bit 1: if set, an end-of-transfer interrupt will be raised after the
memory segment pointed to by this descriptor has been transferred.
The 'id' field corresponds to an identifier of the descriptor.
The 'dest_addr' and 'src_addr' contain the destination and source
addresses to use for the transfer, respectively.
The 'x_len' field contains the number of bytes to transfer,
minus one.
The 'y_len', 'src_stride' and 'dst_stride' fields are only useful for
2D transfers, and should be set to zero if 2D transfers are not
required.
To start a transfer, the address of the first DMA descriptor must be
written to register 0x47c and the HWDESC bit of CONTROL register must
be set. The Scatter-Gather transfer is queued similarly to the simple
transfers, by writing 1 in TRANSFER_SUBMIT.
The Scatter-Gather interface has a dedicated AXI-MM bus configured for
read transfers, with its own dedicated clock, which can be asynchronous.
The Scatter-Gather reset is generated by the reset manager to reset the
logic after completing any pending transactions on the bus.
When the Scatter-Gather is enabled during runtime, the legacy cyclic
functionality of the DMA is disabled.
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
* SPI Engine: Add execution delay documentation
Add documentation for the different delays on the command path and
data path, including communication between submodules and instruction
execution overhead.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
* docs: Improve consistency
The following rules have been implemented:
1. Tables/lists should contain only the carriers that we support for
that reference design.
2. Hexadecimal addresses should be written in caps and separated
by an underscore (eg. 0x9C4A_0000).
3. Block diagrams should contain subtitles only if there are at
least two different diagrams.
4. The GPIOs should be listed in descending order and should have
the number of bits specified next to their name.
5. All the source code links references should contain the project
name.
6. The infrastructure documentation, if exists, should be listed
after the IP list.
* The version is set to be 23.2.0 because this is what Quartus returns
as value when running the --version command
* Still, Quartus has as installation path "intelFPGA_pro/23.2" and not
the version which contains an additional ".0"
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
Recommend storing images like any other artifact: in a hierarchical
manner, without "images" subfolders.
This is intended to avoid dangling artifacts when projects are moved,
renamed, or deleted.
Recommend overwriting the page title with a shorter title in the
toctree, so the navigation bar doesn't overflow or get too cluttered.
Add acostina to CODEOWNERS
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
LBFFilho
PIoandan
Iulia Moldovan
Alin-Tudor Sferle
AndrDragomir
Jorge Marques
laurent-19
IstvanZsSzekely
Jorge Marques
AndreiGrozav
caosjr
Liam Beguin
cristianmihaipopa
Ionut Podgoreanu
StancaPop
Stanca Pop