Commit Graph

36 Commits (cb861f529964f882ac83f4889a07983b211b2b14)

Author SHA1 Message Date
Istvan Csomortani 2e05b70d94 fmcomms11: DMA should use $sys_dma_resetn 2019-06-13 10:59:43 +03:00
Istvan Csomortani 019390f9bf block_design: Updates with new reset net variables 2019-06-11 18:13:06 +03:00
Istvan Csomortani 7960b00684 block_design: Update with new clock net variables
Using the new clock net variables in all Xilinx block designs.
2019-06-11 18:13:06 +03:00
Istvan Csomortani 119fd0915a fmcomms11: Make the lane remapping after the link layer 2019-06-10 11:23:41 +03:00
Istvan Csomortani 5d80aa63b2 fmcomms11: Some cosmetic, no functional change 2019-06-10 11:23:41 +03:00
Istvan Csomortani 94dc848292 fmcomms11: Move the FIFO address variables into system_bd
These variables can vary in function of the available memory resources
of the FPGA carrier board.
2019-06-10 11:23:41 +03:00
Istvan Csomortani 559ae69b2b fmcomms11: Fix DAC data path
Fix the modification 68a5f2.
2019-06-10 11:23:41 +03:00
Istvan Csomortani d9230fdc5e fmcomms11: Connect DAC fifo bypass to a GPIO
GPIO[60] can be used to control the bypass line of the
util_dacfifo module.
2019-06-10 11:23:41 +03:00
Istvan Csomortani 68a5f2f86c fmcomms11: Add a upack module into the TX path
Because the AD9162 will run in M=2 mode, we have to put a upack module
between the TPL and FIFO/DMA.
2019-05-24 11:07:13 +03:00
Istvan Csomortani 7b26190716 fmcomms11: By default we support complex mode 2019-05-16 13:26:58 +03:00
Istvan Csomortani cf03e216fe fmcomms11: Update the project with the new TPL 2019-05-16 13:26:58 +03:00
Istvan Csomortani eba1975144 fmcomms11: Initial commit 2019-05-16 13:26:58 +03:00
Istvan Csomortani 43496cf80a fmcomms11: Move project to a feature branch 2018-04-13 18:22:15 +03:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
Istvan Csomortani b0b79013f7 fmcomms11: Connect data underflow to the core 2017-08-22 09:16:21 +01:00
Lars-Peter Clausen 0360e8587e Connect JESD204 interrupts
Connect the ADI JESD204 link layer peripheral interrupt signals in all
projects.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-05 14:37:50 +02:00
Istvan Csomortani 50cdb6db67 Merge branch 'jesd204' into dev 2017-05-31 20:44:32 +03:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Lars-Peter Clausen 4d00439d52 fmcomms11: Convert to ADI JESD204
Convert the FMCOMMS11 project to the ADI JESD204 link layer cores. The
change is very straight forward, but a matching change on the software side
is required.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Istvan Csomortani 0442e7d404 util_adxcvr: Fix parameter setup at instantiation
If a parameter value is defined as a string binary (e.g. "001001000000"),
it can confuse the tool, and the value may be used as a decimal number.
To prevent this issue and to improve readability converting all the binary
constants into hexadecimal.
2017-04-27 15:35:39 +03:00
Istvan Csomortani 5174bc1f67 fmcomms11: Update IP instantiations 2017-04-21 15:11:25 +03:00
AndreiGrozav d08d1d5a1b adrv9371x ,daq3, fmcomms7, fmcomms11: add dac_fifo missing reset connection 2017-03-10 14:20:42 +02:00
Rejeesh Kutty 6b1a8852a9 dacfifo- bypass port name change 2017-02-27 16:06:39 -05:00
Rejeesh Kutty daa3df4b96 projects/- xcvr updates 2016-11-22 16:23:05 -05:00
Rejeesh Kutty 5731ba3300 fmcomms11- xcvr updates 2016-10-24 09:51:40 -04:00
Istvan Csomortani 3abd87631a fmcomms11: Fix parameter name 2016-10-21 12:49:48 +03:00
Rejeesh Kutty 8314efd4e9 fmcomms11- xcvr updates 2016-09-26 15:19:29 -04:00
Rejeesh Kutty 4532e5c0cb fmcomms11- support iq mode 2016-07-21 11:58:03 -04:00
Rejeesh Kutty c75289be21 fmcomms11- use qpll tx-12g5, cpll rx-6g25 2016-07-19 16:21:49 -04:00
Shrutika Redkar d6243f3d01 update in fmcomms11 tcl and clock constrains 2016-07-18 09:04:13 -04:00
Shrutika Redkar ad491ec04a updated tcl files after inclusion of ad9162 core 2016-06-30 13:26:16 -04:00
Rejeesh Kutty 509f031d58 fmcomms11- updates 2016-06-10 14:20:43 -04:00
Rejeesh Kutty fdc1240cc8 fmcomms11- spi 2016-06-10 14:20:43 -04:00
Rejeesh Kutty 8f00760c13 fmcomms11- initial commit 2016-06-10 14:20:43 -04:00