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3174 Commits (cb861f529964f882ac83f4889a07983b211b2b14)

Author SHA1 Message Date
sergiu arpadi cb861f5299 ad463x: Fix readme 2021-10-26 15:42:57 +03:00
Istvan Csomortani 15a6480601 ad4630_fmc: Initial commit 2021-10-18 16:13:31 +03:00
Mihaita Nagy ff090b60ef daq2/zcu102: Fix the ad9144 data offload to use internal BRAM 2021-10-15 15:03:22 +03:00
Mihaita Nagy 3640c2b584 daq2/kcu105: Fix the ad9144 data offload to use internal BRAM 2021-10-15 15:03:22 +03:00
Mihaita Nagy 6ad54c1056 daq2/kc705: Fix the ad9144 data offload to use internal bram 2021-10-15 15:03:22 +03:00
Mihaita Nagy 907cd613aa daq2/zc706: Increase BRAM utilization to 52% 2021-10-15 15:03:22 +03:00
LIacob106 e34346360d scripts: Add logic for vivado version check 2021-10-12 14:34:11 +03:00
Laszlo Nagy 5db7574dce scripts/adi_board.tcl: For older families stick with axi_interconnect 
SmartConnect has higher resource utilization and worse timing closure
that makes several zed based projects to fail timing.
 2021-10-07 14:18:49 +03:00
Filip Gherman 9295218a64 projects/ad9081_fmca_ebz: Updated makefiles 2021-10-05 16:56:57 +03:00
Laszlo Nagy 51b643b978 Makefile: Fix misc makefiles from projects and library 2021-10-05 14:24:48 +03:00
Laszlo Nagy 3a1babe366 ad9081_fmca_ebz/vck190: Reset GT with HMC7044 lock 
Reset transceiver with a pulse
 2021-10-05 14:09:51 +03:00
Laszlo Nagy 2562aead32 ad9081_fmca_ebz/common: Drive Rx DMA system side with DMA clock 2021-10-05 14:09:51 +03:00
Laszlo Nagy 8d547f31e1 ad9081_fmca_ebz/vck190: Initial version 2021-10-05 14:09:51 +03:00
Laszlo Nagy 6c58a8d1ab ad9081_fmca_ebz/common: Add Versal transceiver support 2021-10-05 14:09:51 +03:00
Laszlo Nagy 56a25afa68 common/vck190: Initial version 2021-10-05 14:09:51 +03:00
Laszlo Nagy 6a681b9e8d common/vmk180_es1: Initial version 2021-10-05 14:09:51 +03:00
Laszlo Nagy 833e5f0aff common/vmk180: Initial version 2021-10-05 14:09:51 +03:00
Laszlo Nagy 2fec1356d6 scripts/adi_project_xilinx.tcl: VCK190 support 2021-10-05 14:09:51 +03:00
Laszlo Nagy 222c5782b6 scripts/adi_project_xilinx.tcl: Install ES1 board from XHUB, make project compile in batch mode 2021-10-05 14:09:51 +03:00
Laszlo Nagy 011c8c1f36 scripts/adi_project_xilinx.tcl: Add VMK180 & VMK180_ES1 support 2021-10-05 14:09:51 +03:00
Laszlo Nagy c22f622599 scripts/adi_board.tcl: Versal support for memory interconnect and irq interconnect 2021-10-05 14:09:51 +03:00
Laszlo Nagy 08c2ce75fe scripts/adi_board.tcl: Switch cpu_interconnect to SmartConnect 2021-10-05 14:09:51 +03:00
Laszlo Nagy aaaba50f83 scripts/project-xilinx.mk: Update target to xsa and cleanup list 2021-10-05 14:09:51 +03:00
LIacob106 0a986f76b8 scripts: QUARTUS_VERSION and PRO_ISUSED can be set in system_project.tcl 2021-10-02 12:34:10 +03:00
Adrian Costina 0a3724e04c s10soc: Update base desgin from ES to production, H-Tile version 2021-09-30 17:40:13 +03:00
Istvan Csomortani 5a3c3c878b ad9213_dual_ebz: Initial commit 
Used ADF4377 SPI configuration CPOL/CPHA 1 for increasing the reliability of the level translators
ad9213_dual_ebz/s10soc: Redesign the address layout

avl_peripheral_mm_bridge 0x0000000 0x0001FFFF
  * sys_gpio_in  0x00000000
  * sys_gpio_out 0x00000020
  * sys_spi      0x00000040
  * sys_gpio_bd  0x000000D0
  * sys_id       0x000000E0

avl_mm_bridge_0 0x00040000 0x0007FFFF
  * ad9213_rx_0.phy_reconfig_0     0x00000000
  * ad9213_rx_0.phy_reconfig_1     0x00002000
  * ad9213_rx_0.phy_reconfig_2     0x00004000
  * ad9213_rx_0.phy_reconfig_3     0x00006000
  * ad9213_rx_0.phy_reconfig_4     0x00008000
  * ad9213_rx_0.phy_reconfig_5     0x0000A000
  * ad9213_rx_0.phy_reconfig_6     0x0000C000
  * ad9213_rx_0.phy_reconfig_7     0x0000E000
  * ad9213_rx_0.phy_reconfig_8     0x00010000
  * ad9213_rx_0.phy_reconfig_9     0x00012000
  * ad9213_rx_0.phy_reconfig_10    0x00014000
  * ad9213_rx_0.phy_reconfig_11    0x00016000
  * ad9213_rx_0.phy_reconfig_12    0x00018000
  * ad9213_rx_0.phy_reconfig_13    0x0001A000
  * ad9213_rx_0.phy_reconfig_14    0x0001C000
  * ad9213_rx_0.phy_reconfig_15    0x0001E000
  * ad9213_rx_0.link_pll_reconfig  0x00020000

avl_mm_bridge_1 0x00080000 0x000BFFFF
  * ad9213_rx_1.phy_reconfig_0     0x00000000
  * ad9213_rx_1.phy_reconfig_1     0x00002000
  * ad9213_rx_1.phy_reconfig_2     0x00004000
  * ad9213_rx_1.phy_reconfig_3     0x00006000
  * ad9213_rx_1.phy_reconfig_4     0x00008000
  * ad9213_rx_1.phy_reconfig_5     0x0000A000
  * ad9213_rx_1.phy_reconfig_6     0x0000C000
  * ad9213_rx_1.phy_reconfig_7     0x0000E000
  * ad9213_rx_1.phy_reconfig_8     0x00010000
  * ad9213_rx_1.phy_reconfig_9     0x00012000
  * ad9213_rx_1.phy_reconfig_10    0x00014000
  * ad9213_rx_1.phy_reconfig_11    0x00016000
  * ad9213_rx_1.phy_reconfig_12    0x00018000
  * ad9213_rx_1.phy_reconfig_13    0x0001A000
  * ad9213_rx_1.phy_reconfig_14    0x0001C000
  * ad9213_rx_1.phy_reconfig_15    0x0001E000
  * ad9213_rx_1.link_pll_reconfig  0x00020000

Connected directly to the h2s_lw_axi_master
  * ad9213_rx_0.link_reconfig      0x000C0000
  * ad9213_rx_0.link_management    0x000C4000
  * ad9213_rx_1.link_reconfig      0x000C8000
  * ad9213_rx_1.link_management    0x000CC000
  * axi_ad9213_0.s_axi             0x000D0000
  * axi_ad9213_1.s_axi             0x000D1000
  * axi_ad9213_dma_0.s_axi         0x000D2000
  * axi_ad9213_dma_1.s_axi         0x000D3800
 2021-09-30 17:40:13 +03:00
Istvan Csomortani 8acf0296af s10soc:ad_cpu_interconnect: Add an avl_address_width attribute 
The default address space for a new bridge is 256 Kbytes. Add an
avl_address_width attribute to the ad_cpu_interoconnect porecess to
define other address space sizes if needed.

The avl_peripheral_mm_bridge will have an 128 Kbyte address space from
address 0x0000.
 2021-09-30 17:40:13 +03:00
David Winter edd2956d58 data_offload: Fix util_[cu]pack offset to TDD syncs 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-09-30 14:45:54 +03:00
David Winter b9554a9a5a ad9081_fmca_ebz: Integrate axi_tdd into zcu102 design 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-09-30 14:45:54 +03:00
stefan.raus 58737e09ba adi_project_intel.tcl: update quartus to 21.2 
Update Quartus version to 21.2.0.

Signed-off-by: stefan.raus <stefan.raus@analog.com>
 2021-09-30 09:53:53 +03:00
stefan.raus cfe0c0ced5 adi_project_xilinx.tcl, adi_ip_xilinx.tcl: update version to 2021.1 
Update vivado version from 2020.2 to 2021.1 in projects and library scripts.
 2021-09-24 12:11:11 +03:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
Robin Getz b38747cefc Make system: Be explicit in license that cover the make/build system 
The build system is covered under a 1 Clause BSD license. Make sure
users are aware.

Signed-off-by: Robin Getz <robin.getz@analog.com>
 2021-09-16 16:50:53 +03:00
David Winter 1766b42a93 ad_mem_asym: Add option to control cascade layout 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-09-15 12:27:49 +03:00
sergiu arpadi 12b7fbb3a3 scripts: Add *.gen to clean list 2021-09-14 16:44:23 +03:00
hotoleanudan cc68bd5198
fmcjesdadc1: Update block design (#743) 
Modified the project such that there is only one data path for the ADC data: deleted one of the JESD tpl instances, one of the cpack instances and one of the dma instances.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
 2021-09-08 17:19:57 +03:00
David Winter 7423ecae14 data_offload: Improve external synchronization 
This commit adds a new synthesis option to the design, that controls
whether an internal clock domain crossing will be generated. Disabling
this option allows you to use a synchronization signal that is
synchronized to the write clock domain externally, and possibly shared
between multiple devices.

The default value retains the old behavior.

Signed-off-by: David Winter <david.winter@analog.com>
 2021-09-08 11:58:01 +03:00
LIacob106 16a93a804b adrv9001[intel]: Add second pair of DMAs 
fix observations for PR
 2021-09-01 15:04:14 +03:00
Iacob_Liviu fec4137046 ad400xx_fmc: Parametrize board select, sampling rate and adc resolution 
fix comments
 2021-09-01 15:03:10 +03:00
Laszlo Nagy b7f34f7bd9 adrv9009zu11eg & common/zcu102 : Fix zynqmp ref clock definition 
The derived clocks of the zynqmp core are not calculated correctly due
rounding issues, instead of 100MHz the value of 99999001 is received
causing warnings during system validation.

This can be fixed/worked around with the proper reference clock
definition.
 2021-08-20 10:46:09 +03:00
Mihaita Nagy b354d517f5 daq2: Connected loose ad9144 dunf flag that fixes the critical warning 2021-08-20 10:38:52 +03:00
Adrian Costina 4cf53f373b Revert "adrv9009zu11eg: Integrate data_offload" 
This reverts commit 78999e154e.
The integration wasn't properly tested
 2021-08-19 21:43:09 +03:00
stefan.raus 1f24344620 Update Quartus version to 20.4 
Update quartus compilation tools from 20.1 to 20.4.
Remove hardcoded version from axi_adrv9001 ip.
 2021-08-12 11:15:01 +03:00
AndreiGrozav b1d2a069e8 adi_make: Update bin build flow for 2020.1 tools 
The 2020.1 Xilinx tools have a different tcl procedures to build the boot.bin
file.
This commit updates the adi_make tcl flow for the new tools. The new
process is not backwards compatible with tools older than 2020 version.
 2021-08-10 17:44:30 +03:00
David Winter e9e278c898 ad9081_fmca_ebz: Remove bypass gpio 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-08-06 11:55:24 +03:00
David Winter 2178191610 ad9081_fmca_ebz: Switch util_dacfifo to data_offload engine 
Memory requirements are the same as with the dacfifo (1 MiB).

Signed-off-by: David Winter <david.winter@analog.com>
 2021-08-06 11:55:24 +03:00
Istvan Csomortani 564ef77588 data_offload: Calculate AXI_ADDRESS_LIMIT automatically 2021-08-06 11:55:24 +03:00
Istvan Csomortani c82b0fb420 data_offload: Delete fifo_dst_rlast 2021-08-06 11:55:24 +03:00
Istvan Csomortani 4026f2d414 daq2/zc706: PL DDR size is 1GByte 2021-08-06 11:55:24 +03:00
Istvan Csomortani 703cc8a17e data_offload_bd: Calculate the address limit from the address width 2021-08-06 11:55:24 +03:00