4f0accbbfa
adrv9371x fix dacfifo name
2017-05-18 12:54:14 -04:00
ebeebdddf0
altera- infer latest versions
2017-05-12 13:40:14 -04:00
6ed721ee66
adrv9371/a10soc: Integrate the avl_dacfifo into project
2017-04-21 13:27:35 +03:00
8f1564a9c4
adrv9371x/a10gx- gpio matching
2017-03-27 13:51:45 -04:00
762276a880
adrv9371x- dacfifo changes
2017-03-06 10:33:52 -05:00
bc6a09c828
adrv9371x/a10soc- dacfifo added
2017-03-01 15:35:04 -05:00
2d7fb03b93
adrv9371x/a10gx- fix os xcvr parameters
2016-12-06 12:31:40 -05:00
f752f0c9d7
a10soc- xcvr updates
2016-10-27 09:25:00 -04:00
e40311eee9
adrv9371x: A10soc, connected DMAs through 128 bit SDRAM0 port at 175MHz
2016-09-29 09:14:37 +01:00
f5809b8817
adrv9371x: a10soc, added adcfifos; connected the new reset to all peripherals; used the new f2sdram1 port
2016-09-24 10:09:05 +03:00
521c41ce32
adrv9371x: Updated a10soc project. Common design differentiates between nios and a10soc carrier
2016-09-08 11:44:45 +03:00
d18f6aa816
adrv9371x: A10GX, added adcfifo
...
- connected dac dma to 133 MHz clock
- set explicit clock rate to xcvr reference clock bridge
2016-08-26 14:46:48 +03:00
215edb11c6
adrv9371: A10GX, updated design
...
- disable reconfiguration for RX transceivers and enabled the reconfiguration for TX transceiver. They cannot be enabled at the same time at this point
- update FIFO SIZE to 16 for all DMAs
- updated memory connections to 256 bit and moved clock connection to 133 MHz, for all DMAs.
2016-08-23 18:25:48 +03:00
41203d07e9
adrv9371x: A10GX, update SPI connection
2016-08-18 17:42:27 +03:00
5c27ccd1fa
adrv9371x: Added common qsys tcl
2016-08-16 15:34:10 +03:00
Rejeesh Kutty
Istvan Csomortani
Adrian Costina