Rejeesh Kutty
|
cc6bf53d98
|
adrv9371x/a10soc- altera reset synchronizer false path?
|
2017-03-23 09:46:40 -04:00 |
Adrian Costina
|
968d94603e
|
fmcjesdadc1: Update xcvr configuration to the default one used for this board
|
2017-03-23 11:31:00 +02:00 |
|
Rejeesh Kutty
|
4a275302a0
|
a5soc- add ddr3 location assignments
|
2017-03-22 10:12:34 -04:00 |
|
Rejeesh Kutty
|
7e87ecae22
|
altera/a10gx- daq1/fmcomms2 fix typos
|
2017-03-22 09:48:02 -04:00 |
|
Rejeesh Kutty
|
b3f06af77a
|
altera srf files do not work
|
2017-03-22 09:25:50 -04:00 |
|
Rejeesh Kutty
|
66a5d44a18
|
a5gte- add constraints for tq
|
2017-03-21 10:53:31 -04:00 |
|
Rejeesh Kutty
|
2e22ce3b62
|
a10gx- ignore preliminary timing model warnings
|
2017-03-21 10:52:28 -04:00 |
|
Rejeesh Kutty
|
d84e34fe5f
|
arradio/c5soc- reset false path for vga dma
|
2017-03-21 10:15:38 -04:00 |
|
Rejeesh Kutty
|
8063ba2b66
|
make updates
|
2017-03-20 16:05:18 -04:00 |
|
Rejeesh Kutty
|
c7351f3ce3
|
arradio/c5soc- remove qsys files
|
2017-03-20 15:56:07 -04:00 |
|
Rejeesh Kutty
|
589e6b53d8
|
arradio/c5soc- qsys-script flow
|
2017-03-20 15:42:33 -04:00 |
|
Rejeesh Kutty
|
b39fecadd9
|
altera- ignore preliminary timing messages
|
2017-03-20 12:48:53 -04:00 |
|
Rejeesh Kutty
|
7dfa8c599f
|
arradio/c5soc- updated to new framework/16.0
|
2017-03-20 12:15:18 -04:00 |
|
Rejeesh Kutty
|
12f44ccbcc
|
arradio/c5soc- critical warnings fix
|
2017-03-20 12:14:21 -04:00 |
|
Rejeesh Kutty
|
9b6dd27c23
|
ad9361- delay initialization
|
2017-03-15 12:06:59 -04:00 |
|
Adrian Costina
|
09bcecb6ed
|
m2k: Simplify DMA connection to HP1
|
2017-03-15 15:11:30 +02:00 |
|
Adrian Costina
|
2a9b3cea09
|
m2k: Changed the way DMAs connect to the PS7 DDR, to optimize resources use
|
2017-03-14 13:57:50 +02:00 |
|
Adrian Costina
|
f7c2bd943b
|
m2k: Enable AD9963 adc data path processing.
- part of the path is the sign extension module. Without it, the triggering doesn't work correctly
|
2017-03-13 23:18:29 +02:00 |
|
Rejeesh Kutty
|
c3c8c366d3
|
axi_ad9361- add receive init delay
|
2017-03-13 16:28:53 -04:00 |
|
Rejeesh Kutty
|
dac75f79ab
|
fmcomms5/usrpe31x- add iodelay report
|
2017-03-10 13:38:27 -05:00 |
|
Rejeesh Kutty
|
1b3f752c3d
|
pzsdr1/pzsdr2/pluto- add iodelay report
|
2017-03-10 12:55:22 -05:00 |
|
Rejeesh Kutty
|
0ae79ca7ac
|
move/rename - delay script belongs to ad9361
|
2017-03-10 12:44:32 -05:00 |
AndreiGrozav
|
e736504e0f
|
fmcjesdadc1, usdrx1: Using the same clock in rx_data path
|
2017-03-10 14:26:51 +02:00 |
|
AndreiGrozav
|
d08d1d5a1b
|
adrv9371x ,daq3, fmcomms7, fmcomms11: add dac_fifo missing reset connection
|
2017-03-10 14:20:42 +02:00 |
|
Rejeesh Kutty
|
452e5e5ce0
|
fmcomms2- add delay reporting for iodelay
|
2017-03-09 15:29:15 -05:00 |
|
Rejeesh Kutty
|
8bdfbe2b0a
|
fmcomms2- report delays
|
2017-03-09 15:21:42 -05:00 |
|
AndreiGrozav
|
7e5d8664ad
|
fmcjesdadc1_a5gt: rx_data pins are all associated to the same clock
|
2017-03-09 08:57:03 +02:00 |
|
AndreiGrozav
|
0e002f2f31
|
daq3_a10gx: Set XCVR Tx/RX clk/data voltage levels at 1V
|
2017-03-09 08:50:55 +02:00 |
Istvan Csomortani
|
191669ad28
|
daq2_common: Fix the dac_rst for DAC FIFO
|
2017-03-07 16:13:46 +02:00 |
|
Rejeesh Kutty
|
fc8af6903f
|
pzsdr2/ccfmc- add rf input protection
|
2017-03-06 16:19:55 -05:00 |
|
Rejeesh Kutty
|
3fa9a30f0e
|
a10soc/plddr4- lower mem clk to meet timing
|
2017-03-06 14:12:25 -05:00 |
|
Rejeesh Kutty
|
38a27d02f6
|
a10soc/plddr4- differential refclk
|
2017-03-06 14:11:36 -05:00 |
|
Rejeesh Kutty
|
936c441763
|
adrv9371x- dacfifo bypass-gpio control
|
2017-03-06 10:35:09 -05:00 |
|
Rejeesh Kutty
|
762276a880
|
adrv9371x- dacfifo changes
|
2017-03-06 10:33:52 -05:00 |
|
Istvan Csomortani
|
4a6fe54fcf
|
daq2_common: Update common scripts
Add new port connection for util_dacfifo
|
2017-03-03 18:49:10 +02:00 |
|
Rejeesh Kutty
|
ec89b1a45f
|
altera/adrv9371x- add dacfifo
|
2017-03-01 15:52:07 -05:00 |
|
Rejeesh Kutty
|
bc6a09c828
|
adrv9371x/a10soc- dacfifo added
|
2017-03-01 15:35:04 -05:00 |
|
AndreiGrozav
|
5b5c0dde99
|
ad6676evb: Set default xcvr parameters to common design
|
2017-03-01 11:32:17 +02:00 |
|
AndreiGrozav
|
b78e9d8c27
|
daq2_a10gx: Set XCVR Tx/RX clk/data voltage levels at 1V
|
2017-03-01 11:32:17 +02:00 |
|
AndreiGrozav
|
0cc5130c9a
|
adrv9371x: Set XCVR Tx/RX clk/data voltage levels at 1V
|
2017-03-01 11:32:17 +02:00 |
|
AndreiGrozav
|
c1be17a3af
|
Altera a10 devices: disable warnings regarding unused channels
|
2017-03-01 11:32:17 +02:00 |
|
AndreiGrozav
|
dc168f41fe
|
adrv9371_a10soc: Fixed port assignments
|
2017-03-01 11:32:17 +02:00 |
|
Rejeesh Kutty
|
aad41039bd
|
a10soc- plddr4 settings
|
2017-02-28 13:36:28 -05:00 |
|
Adrian Costina
|
59dda01419
|
m2k: Disabled DDS cores for the generic project
|
2017-02-28 10:10:28 +02:00 |
|
Rejeesh Kutty
|
fb4a583613
|
projects/system_bd- adc/dac fifo board designs
|
2017-02-27 16:06:39 -05:00 |
|
Rejeesh Kutty
|
6b1a8852a9
|
dacfifo- bypass port name change
|
2017-02-27 16:06:39 -05:00 |
|
Rejeesh Kutty
|
19c7b5d340
|
fmcadc5- move adc fifo settings to system-board
|
2017-02-27 16:06:39 -05:00 |
|
Rejeesh Kutty
|
c1aac4a9fb
|
common: adc/dac fifo board designs
|
2017-02-27 16:06:39 -05:00 |
|
Adrian Costina
|
545e458997
|
m2k: Standalone, ignored critical warning for contraints that should only be applied at the implementation stage
|
2017-02-27 14:17:29 +02:00 |
|
Adrian Costina
|
eda585f0e4
|
m2k: Connected data[0] and trigger[0] pins to the logic analyzer clock generator input 2
|
2017-02-27 14:16:32 +02:00 |