5 Commits (cd163e36c7e512a4e4045f1fc41d3d67b3f3b082)

Author	SHA1	Message	Date
Adrian Costina	2fc5d08c0b	axi_gpreg: Fixed constraints	2017-06-13 14:04:43 +03:00
Istvan Csomortani	ac2e5a9dac	constraints: Update constraints ... Xilinx recommends that all synchronizer flip-flops have their ASYNC_REG property set to true in order to preserve the synchronizer cells through any logic optimization during synthesis and implementation.	2017-02-24 13:43:32 +02:00
Rejeesh Kutty	839e76996f	axi_gpreg: added constraints	2015-11-05 11:28:37 -05:00
Rejeesh Kutty	ad1cef1441	axi_gpreg: compile fixes	2015-11-03 14:29:00 -05:00
Rejeesh Kutty	c8019b69fd	axi_gpreg- added	2015-11-03 14:28:59 -05:00