d6c64e031f
axi_hdmi_rx: Drop TPG enable from register map
...
The TPG is no longer part of the RX core and the corresponding bit in the
register map isn't hooked up to anything. So drop it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
542d64bb5a
up_hdmi_rx: Fix enable control
...
Connect the enable signal in the register map to the up_preset signal so
that it is possible to enable/disable to core at runtime.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
231a21548c
up_hdmi_rx: Fix TPM OOS clear
...
The TPM OOS status flag is in bit 1. Make sure writing to bit 1 rather than
bit 0 clears the TPM OOS.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
330c205e8e
fmcjesdadc1- sys_clk changes
2015-06-30 10:47:21 -04:00
185e489802
cpack- signaltap mess
2015-06-29 16:31:53 -04:00
6bc24e25eb
stap- need to be qsys
2015-06-29 13:26:32 -04:00
d25e02d7ee
stap- need to be qsys
2015-06-29 13:26:20 -04:00
aef6f6b20b
imageon: Hdmi_iic_rstn is accessible through a GPIO.
...
Connect hdmi_iic_rstn to GPIO[33]
2015-06-29 10:48:57 +03:00
6862655b0d
Add .gitattributes file
...
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
543e08b67a
fmcadc1: sdc updates
2015-06-25 04:25:39 -04:00
c0dd80ccee
axi_hdmi_rx: Fix alignment issue on packed formats
...
Some cases, when software changed the image formats, the packed formats (24bit/pixel) lost alignment.
(the first 32 bit after sof got lost) This commit fix that issue.
2015-06-24 12:43:55 +03:00
15740a7d34
fmcjesdadc1- 15.0 updates
2015-06-24 05:31:09 -04:00
281a47c117
bsplit- altera version, avalon needs a clock
2015-06-24 05:31:08 -04:00
f4a1a5817c
jesd-align: allow sof pass through -- qsys can only do 1 src-dest
2015-06-24 05:31:06 -04:00
e1b1e1bc2c
ad9250- update to use alt ip interface script
2015-06-24 05:31:04 -04:00
00bc48bc24
axi_hdmi_rx: Fix synchronization issues
2015-06-24 11:03:39 +03:00
4e30a5b0bf
axi_ad9250: Updated altera core to work with axi4lite interface
2015-06-23 14:29:23 +03:00
714d415804
daq2/a10gx- signaltap changes
2015-06-19 14:33:04 -04:00
3e5a5504a7
library/jesd-align- remove signaltap interface
2015-06-19 14:33:03 -04:00
af2ffbe0a0
library/cpack- add signaltap
2015-06-19 14:33:02 -04:00
ac6e28c461
library/common: add altera signaltap
2015-06-19 14:33:01 -04:00
51e6a74a3d
daq2/a10gx- add xmit swap
2015-06-19 14:32:59 -04:00
d6b1260678
daq2/a10gx- signal tap + gpio
2015-06-19 14:32:58 -04:00
8a52631189
libary: util_jesd_align- signal tap interface
2015-06-19 14:32:57 -04:00
7e08ff0422
library: added util_jesd_xmit
2015-06-19 14:32:56 -04:00
67df6b3ea8
a10gx- disable lab cell on dsp input register
2015-06-19 14:32:54 -04:00
db76fe3298
tquest- generate the timing report file
2015-06-19 14:32:53 -04:00
c3ea99d1f8
fmcadc2: Fixed zc706 spi connection
2015-06-19 13:31:59 +03:00
ad743c8403
axi_ad9434: This IP core does not have 'data underflow' port
2015-06-18 16:51:42 +03:00
301226c766
fmcjesdadc1: Fixed mdc_mdio connection for kc705
2015-06-18 11:06:47 +03:00
f01ba54c5f
fmcomms1: Fixed mdc_mdio connection for kc705
2015-06-18 11:06:33 +03:00
009d33f0a0
ad9467: Fixed mdc_mdio connection for kc705
2015-06-18 11:06:20 +03:00
2e46bda916
motcon2_fmc: Update project to use the latest util_gmii_to_rgmii
2015-06-16 17:43:10 +03:00
d137811952
util_gmii_to_rgmii: Updated core so that it has an option to include a delay controller.
...
It also allows to configure the fixed delay value so that no additional constraints are needed
The default value of 18 seems to work very well(450mbps tx / 640 mbps rx) on the motor control platform used for tests
2015-06-16 17:39:31 +03:00
8fc0e0e62d
fmcjesdadc1: Fixed vc707 ethernet connections
2015-06-16 16:27:09 +03:00
142f802f54
adv7511: Fixed vc707 ethernet connections
2015-06-16 16:26:58 +03:00
4c80013faf
projects/daq2: gt lane split
2015-06-12 15:56:03 -04:00
28e8275a5d
library/axi_jesd_gt: split gt lanes
2015-06-12 15:56:03 -04:00
e6525136a9
daq2/common: axi_ad9144_fifo needs a proper reset sequence
...
Connect the axi_ad9144_fifo/dma_rst signal to sys_cpu_reset
2015-06-12 14:03:46 +03:00
ddc08c960c
ad_tdd_control: Connect the reset to all the flops
2015-06-11 12:07:47 +03:00
f587aa42d9
a10gx- tx sync
2015-06-10 14:32:25 -04:00
04eb998ff1
axi_jesd_gt: constraints
2015-06-10 14:29:06 -04:00
e3e4af5c51
daq2/zc706: open ports
2015-06-10 14:25:58 -04:00
e2f4a4c5cf
library: make preset registered for timing paths
2015-06-10 13:41:41 -04:00
df0eaad1e2
gt: constraints
2015-06-10 11:38:15 -04:00
97ab5e0ef7
fmcomms1: Update project to integrate the new util_wfifo
2015-06-10 15:16:17 +03:00
8a1f4bf5f6
ad6676,ad9144,ad9152,ad9234,ad9250,ad9434,ad9467,ad9625,ad652,ad9671,ad9680,ad9739a:Set default driver value for overflow, underflow, gpio_in and dac_sync ports
2015-06-09 14:21:12 +03:00
00b8c171b8
a10gx: pll locked to reset controller
2015-06-08 15:00:11 -04:00
a598e1c614
axi_ad9265: Set default driver value for overflow and underflow ports
2015-06-08 17:50:23 +03:00
ccf887f0ba
axi_ad9643: Set default driver values for overflow, underflow and gpio_in ports
2015-06-08 17:48:41 +03:00
Lars-Peter Clausen
Rejeesh Kutty
Istvan Csomortani
Adrian Costina