Commit Graph

18 Commits (cd6024b34172a66edf315bda3ffea529feb56d21)

Author SHA1 Message Date
AndreiGrozav ebae8bf8c1 Remove interrupts from system_top for all xilinx projects
- remove interrupts from system_top
- for all suported carriers:
	- remove all interrupt bd pins
	- connect to GND all initial unconnected interrupt pins
- update ad_cpu_interrupt procedure to disconnect a interrupt from GND
before connectiong it to another pin.
2018-08-10 10:10:58 +03:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
Adrian Costina 98b58562d6 system_top: Non functional changes in system_tops to reduce warnings
Loop back the unused GPIO pins, and add all the SPI interface to system
wrapper instance.

The following system_top modules were changed:
  - ad738x_fmc
  - ad7616_sdz
  - ad77681evb
  - ad77681evb
  - ad7768evb
  - ad9739a_fmc
  - ad9434
  - adrv9739
  - fmcadc5
  - ad6676evb
  - ad9265
  - ad5766
  - fmcomms5
  - m2k
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 0360e8587e Connect JESD204 interrupts
Connect the ADI JESD204 link layer peripheral interrupt signals in all
projects.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-05 14:37:50 +02:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
Istvan Csomortani 67390c2a95 ad6676evb: Update projects with ad_sysref_gen 2016-12-19 10:52:25 +00:00
Istvan Csomortani c0b0f9b7e9 ad6676evb: Connect SYS_REF to GPIO 2016-12-14 17:55:50 +02:00
Istvan Csomortani d6918de19e ad6676: Update projects to xcvr frame work 2016-11-10 10:39:46 +02:00
Adrian Costina c196b5bf68 ad6676evb: VC707, fixed system top gpio_bd datawidth 2016-10-05 15:50:43 +03:00
Adrian Costina ab4b73fd32 ad6676evb: Updated VC707 project 2015-09-25 16:07:22 +03:00
Rejeesh Kutty a6cae6b477 iobuf: do is a system verilog keyword 2015-05-21 14:06:17 -04:00
Rejeesh Kutty 8f2fdec838 ad6676evb/vc707: 2014.4 updates 2015-03-30 14:59:09 -04:00
Istvan Csomortani 5e70ef4ab9 ad6676ebv_vc707: Update the interrupts 2014-11-26 10:49:14 +02:00
Istvan Csomortani 72f9dd226a ad6676evb_vc707: Add support for linear flash 2014-11-26 10:48:27 +02:00
Rejeesh Kutty 3211964c2e ad6676evb: added 2014-11-10 13:41:01 -05:00