c926daca3a
ad9361/tdd: Fix generation of tx_valid_* signals
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In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of
the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals.
In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
2015-06-08 16:22:21 +03:00
6338dfd8b7
ad9361: ip defaults & rst output
2015-06-05 09:19:39 -04:00
2e877389b2
ad9361_tdd: Some naming and hierarchical changes
2015-06-04 18:09:49 +03:00
3b1ea7e528
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch
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598ece4c8d
2015-06-04 18:09:47 +03:00
2bad47cf4f
delay-cntrl: up-clk, direct access + tx
2015-05-18 14:28:20 -04:00
2e7135c3c2
axi_ad9361_tdd: Initial commit.
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Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 12:20:44 +03:00
32f7e98afd
ad9361: add ddr-edgesel
2015-05-06 16:58:47 -04:00
ee0912eb6a
ad9361: make 2t2r external for mw
2015-01-05 10:54:23 -05:00
de33722470
up/constr: independent read/write and local constraints
2014-10-02 14:35:59 -04:00
3162540b03
axi_ad9361: Remove the Altera toplevel wrapper
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By setting the AXI controler interface type from axi4 to axi4lite we can use
the normal toplevel file with only a simple modification to add the awprot
and arprot signals.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:29:13 +02:00
41cc92ef49
Remove BASEADDR/HIGHADDR parameters
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This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
50faf0c53a
Remove executable flags from non-exectuable files
2014-09-09 15:05:06 +02:00
c0e31aa6c2
daq2: latest hardware
2014-07-21 09:06:57 -04:00
b6052773b7
added adc/dac gpio registers
2014-06-27 14:45:58 -04:00
10a7804e14
ad9361: altera wrapper updates
2014-06-25 15:26:06 -04:00
e650253013
library: register map changes and for mathworks
2014-06-24 14:22:05 -04:00
bef6a9c32c
axi_ad9361: Split dma data into individual channels for both ADC and DAC
2014-06-07 17:15:31 +03:00
5b5bca400f
ad9361: added adc loopback
2014-05-27 14:47:59 -04:00
842cd98b61
ad9361: adc loopback option
2014-05-27 12:15:02 -04:00
3aed3ba71c
axi_ad9361: fmcomms5 changes
2014-05-19 12:41:12 -04:00
570ec26798
FMCOMMS2: Added sync option
2014-04-11 18:14:48 +03:00
5aac9d7288
FMCOMMS2 added sync option
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Added signals to allow synchronisation of multiple AD9361.
2014-04-10 10:46:42 +03:00
ad491e92ab
changed pcore version and made it local (top shouldn't override)
2014-03-14 12:02:16 -04:00
580808e146
axi_ad9361: added
2014-03-11 20:01:55 -04:00
Istvan Csomortani
Rejeesh Kutty
Lars-Peter Clausen
Adrian Costina
ATofan